Dual Vertical Transfer Gate Layout for CMOS Charge Backflow Control
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Solution Overview
Problem
CMOS image sensing devices face challenges in efficiently transferring negative charges due to potential hump issues and backflow phenomena caused by electric field concentration between gate poles, particularly as device size decreases, leading to reduced charge transfer efficiency and complex fabrication processes.
Innovation Solution
Incorporating a first insulating pattern, such as a composite layer of silicon nitride or silicon oxide, between the gate poles and the substrate to reduce electric field strength and prevent charge transfer hindrance, while using a dual vertical transfer gate with connecting poles to enhance charge transfer efficiency and simplify the interconnection structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dual vertical transfer gate with connecting poles is used, then charge transfer efficiency is improved, but electric field concentration between poles causes potential hump and backflow issues
Solution Approach 1:
An insulating pattern is introduced as an intermediary element between the gate poles to modify the electric field distribution. This insulating layer prevents direct electric field concentration between the poles, thereby eliminating potential hump and backflow issues while preserving the charge transfer efficiency provided by the dual vertical gate structure.
Solution Approach 2:
The insulating pattern is locally positioned between the gate poles where electric field concentration occurs. This localized modification changes the electric field properties only in the critical region between poles, maintaining the overall vertical gate functionality while preventing harmful field concentration effects.
2Area of stationary object
If device size is reduced for high density, then device integration is improved, but charge transfer efficiency deteriorates
Solution Approach 1:
The transfer gate structure transitions from a planar configuration to a vertical three-dimensional structure with poles extending downward. This dimensional change allows the gate to achieve effective charge transfer control in a smaller planar footprint, enabling high device density while maintaining charge transfer efficiency through the vertical field configuration.
3Object-affected harmful factors
If insulating pattern is added between gate poles and substrate, then electric field concentration is reduced, but fabrication complexity increases
Solution Approach 1:
The insulating pattern is merged with the existing gate pole fabrication process. The insulating material is deposited and patterned together with the gate electrodes in the same manufacturing sequence, combining multiple functions into a unified fabrication flow and avoiding additional complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents charge transfer hindrance and backflow issues, improving charge transfer efficiency and simplifying the fabrication process, especially in high-density, miniaturized image sensing devices, by reducing electric field concentration and simplifying the interconnection structure.
Implementation Method 1
electric field concentrated to an inter-pole region between a pair of poles
Data Source
AI summary
A dual vertical transfer gate, a transistor including the same, and a CMOS image sensing device including the same. In some embodiments, a gate of the dual vertical transfer transistor may include a pair of poles, which are extended to an n-type region of a photodiode, and a connecting portion, which connects the paired poles to each other. A first insulating pattern may be provided between the poles and on the substrate.