Semiconductor Chip Sidewall Structure for Low-Defect Wafer Separation
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Solution Overview
Problem
The increasing miniaturization and performance of semiconductor chips in semiconductor packages lead to higher difficulty in preventing defects such as cracking, kinking, and peeling during wafer division, which in turn reduces productivity.
Innovation Solution
A semiconductor device and manufacturing method that involve forming a groove in the wafer using a laser and applying tension to separate the wafer portions, with a heat affected zone formed to enhance the strength of the semiconductor chip and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor chips are miniaturized and performance is increased, then chip size is reduced and performance is improved, but difficulty in preventing defects during wafer division increases
Solution Approach 1:
A groove is formed in the wafer before wafer division using laser processing. This preliminary action creates a predetermined separation path that guides the division process, preventing defects such as cracking and peeling that would otherwise occur during chip separation. The groove acts as a pre-prepared weak point that facilitates clean separation without compromising chip integrity.
Solution Approach 2:
A groove is introduced as an intermediary structure between adjacent semiconductor chips on the wafer. This groove serves as a mediator that enables clean separation of miniaturized chips without directly affecting the chips themselves. The groove absorbs the mechanical stress during division, preventing transmission of forces that would cause defects in the miniaturized chips.
2Ease of manufacture
If conventional wafer division methods are used, then manufacturing process is simple, but defects such as cracking, kinking, and peeling occur
Solution Approach 1:
The conventional mechanical wafer division method is replaced with laser-based groove formation followed by tension application. Instead of using mechanical sawing or dicing that directly contacts and stresses the chips, the laser creates a groove and then tension is applied to separate portions along the groove path. This substitution eliminates mechanical contact with the chips, preventing cracking and kinking while maintaining ease of manufacture.
3Reliability
If laser groove formation and tension application are used, then defect prevention is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process utilizes parameter changes in the laser system to form grooves with specific characteristics. By controlling laser power, pulse duration, and scanning speed, grooves with optimal depth and geometry are created that facilitate clean separation. This parameter control enables defect prevention without requiring additional process steps or complex equipment, as the laser parameters are adjusted within existing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents defects in semiconductor chips and enhances productivity by improving the strength and reducing the likelihood of cracks and other defects during wafer division.
Implementation Method 1
forming a groove in a front surface of a wafer using a laser
Implementation Method 2
a first side surface of the semiconductor chip from a point on a side surface of the substrate to an edge of a front surface of the semiconductor chip has a heat affected zone
Implementation Method 3
separating a plurality of portions of the wafer connected to each other with the groove therebetween by applying tension to the wafer so that the plurality of portions are spaced apart from each other
Data Source
AI summary
A semiconductor package includes a semiconductor chip including a substrate, an interconnection structure on a front surface of the substrate, and a pad layer on a front surface of the interconnection structure. A first side surface of the semiconductor chip from a point on a side surface of the substrate to an edge of a front surface of the semiconductor chip is oblique to, or more curved than, the front surface of the semiconductor chip, and is oblique to, or more curved than, a second side surface of the semiconductor chip from the point to an edge of a back surface of the semiconductor chip.