ESD Protection Layout With Dual Wells for Low Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ESD protection circuits for high-frequency circuits suffer from increased signal loss due to parasitic capacitors, and existing solutions either increase manufacturing costs or device size.
Innovation Solution
The electrostatic discharge protection device features a semiconductor substrate with adjacent first and second well regions of a first conductivity type, along with heavily doped regions of different conductivity types. The well regions have different doping concentrations and profiles, allowing for reduced parasitic capacitance without additional masks or process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits using diodes are used in high-frequency circuits, then electrostatic discharge protection is provided, but parasitic capacitors cause signal loss and deteriorate RF circuit performance
Solution Approach 1:
The patent changes the structural parameters of the ESD protection circuit by using well regions with different doping concentrations and different bottom profiles (first bottom and second bottom). This parameter optimization reduces the parasitic capacitance of the protection circuit, thereby reducing signal loss in high-frequency applications while maintaining ESD protection capability.
2Loss of energy
If additional masks or process steps are used to reduce parasitic capacitance, then signal loss is reduced, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent merges the formation of well regions with different doping concentrations and different bottom profiles into a single integrated structure that can be formed using existing manufacturing processes. The first well region and second well region are both formed in the semiconductor substrate without requiring additional masks or process steps, thereby reducing parasitic capacitance while maintaining manufacturing simplicity.
3Loss of energy
If well regions with different doping concentrations and profiles are used, then parasitic capacitance is reduced, but device size may increase
Solution Approach 1:
The patent applies local quality by creating well regions with different doping concentrations and different bottom profiles at specific locations within the semiconductor substrate. The first well region has a first doping concentration and first bottom profile, while the second well region has a second doping concentration and second bottom profile. This localized optimization reduces parasitic capacitance in critical areas without unnecessarily increasing the overall device size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces signal loss in high-speed applications while maintaining a small device size, improving manufacturing efficiency and accuracy without increasing costs.
Implementation Method 1
The first well region and the second well region have different doping concentrations. The first well region is formed by diffusing a portion of first dopants in the first doped region into the first discontinuous portion.
Implementation Method 2
An electrostatic discharge (ESD) is a phenomenon that releases and transfers charges between a semiconductor device (e.g., a semiconductor chip) and an external object (e.g., a human body).
Implementation Method 3
The method further includes performing an annealing process to form a first well region from the first doped region and a second well region from the second doped region, wherein the first well region is formed by diffusing a portion of first dopants in the first doped region into the first discontinuous portion.
Data Source
AI summary
An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, first and second well regions, and first and second heavily doped regions. The first and second well regions have a first conductivity type and are located in the semiconductor substrate. The first heavily doped region on the first well region has a second conductivity type. A first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles. The first and second well regions have different doping concentrations. The second heavily doped region on the second well region has the first conductivity type. The first and second heavily doped regions are arranged side-by-side and are spaced apart from each other. The first heavily doped region is electrically connected to an input/output terminal.