3D Memory Cell Stack Alignment for Reliable Semiconductor Storage
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high reliability due to the limitations of two-dimensional memory cell arrangements, which hinder the increase in data storage capacity.
Innovation Solution
The semiconductor device incorporates a three-dimensional arrangement of memory cells, featuring a semiconductor layer with stacked gate electrodes and channel structures, along with a mold structure that includes interlayer insulating layers and sacrificial layers, optimized to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory cell arrangement is used, then manufacturing process is simpler, but data storage capacity cannot be increased sufficiently
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked gate electrode structures. Multiple gate electrodes are stacked vertically to form multi-layer memory cells, enabling increased storage capacity by utilizing the vertical dimension. This dimensional change allows more memory cells to be packed within the same planar area, directly addressing the limitation of two-dimensional arrangements.
2Quantity of substance
If three-dimensional stacked gate electrodes are implemented, then data storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces align key structures that are formed in advance during the manufacturing process. These align keys serve as reference markers that guide the precise alignment of stacked gate electrodes and other vertical structures. By establishing alignment references beforehand, the manufacturing process can achieve the required precision for three-dimensional stacked structures without increasing overall process complexity.
3Reliability
If align key structure is optimized to prevent overlap, then reliability improves, but device complexity increases
Solution Approach 1:
The patent extracts the alignment function into separate align key structures that are distinct from the functional mold structures. By separating the alignment reference function from the structural support function, the patent prevents overlap between interlayer insulating layers/sacrificial layers and align keys. This extraction improves reliability by ensuring proper alignment without requiring the mold structures to be overly complex.
Data Source
AI summary
A semiconductor device includes gate electrodes stacked in a first region to form a first stack structure and a second stack structure, a channel structure penetrating through the first and second stack structures, a first mold structure in a second region, an align key structure penetrating through the first mold structure, and a second mold structure on the first mold structure and the align key structure. The second mold structure includes a first interlayer insulating layer, a first horizontal sacrificial layer, a second interlayer insulating layer, and a second horizontal sacrificial layer sequentially stacked on an upper surface of the first mold structure, the first interlayer insulating layer and the first horizontal sacrificial layer are spaced apart from the align key structure in a horizontal direction, and the second interlayer insulating layer covers an upper surface and a portion of a side surface of the align key structure.