Stacked Memory Through-Via Switching for Variable Pin Bandwidth
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Solution Overview
Problem
High bandwidth memory devices face challenges in accommodating varying numbers of data input/output pins and data transfer rates to match interconnectivity with external devices, which limits their configurability and increases costs related to size and pitch configurations.
Innovation Solution
A memory device architecture that includes stacked core dies and a base die with through-vias, utilizing a multiplexer to adjust data output based on mode signals, allowing for flexible data exchange and reducing the number of data bumps, thereby accommodating different data transfer rates and pin configurations without altering the device configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of data input/output pins and data transfer rate are fixed at high values, then the memory device achieves high bandwidth performance, but it cannot accommodate external devices with varying pin counts and transfer rates
Solution Approach 1:
The patent implements dynamic configurability by introducing a mode signal that controls a multiplexer to switch between different data transfer modes (e.g., 8-bit, 16-bit, 32-bit widths and different transfer rates). This allows the memory device to adapt its pin configuration and data transfer rate dynamically based on the connected external device, resolving the contradiction between fixed high-performance configuration and adaptability to varying device requirements
Solution Approach 2:
The memory device achieves multi-functionality by designing a universal interface that can operate with external devices having different numbers of pins and different data transfer rate requirements. Through the mode signal-controlled multiplexer, a single physical configuration can serve multiple external device types, eliminating the need for multiple fixed configurations
2Productivity
If the memory device is designed with fixed high values for data input/output pins and transfer rate, then high bandwidth is achieved, but cost increases for size and pitch configurations
Solution Approach 1:
The patent changes operational parameters dynamically through the mode signal that controls the multiplexer. By switching between different data widths (8-bit, 16-bit, 32-bit) and transfer rates based on external device capabilities, the system achieves high bandwidth when needed while reducing to lower configurations when external devices have fewer pins or lower transfer rate requirements, thereby reducing manufacturing costs for size and pitch configurations
3Reliability
If the memory device uses a fixed configuration with high number of data input/output pins, then high bandwidth performance is maintained, but compatibility with external devices having fewer pins is limited
Solution Approach 1:
The system dynamically adjusts its operational configuration through the mode signal-controlled multiplexer to match the capabilities of connected external devices. When a high-bandwidth device is detected, the system operates at full pin count and transfer rate; when a device with fewer pins or lower transfer rate is detected, the system automatically reduces its configuration, ensuring reliable operation across diverse device types while maintaining optimal bandwidth performance
Data Source
AI summary
The present disclosure relates to memory devices and memory systems. An example memory device includes a first core die, a second core die, and a base die stacked in a first direction. The base die is configured to output data of memory cells provided by the first and second core dies through a through-via. The through-via passes through the first and second core dies in the first direction with different burst lengths based on a mode signal.