Mixed-Height Cell Rows With Variable Nanoribbons for Lower Parasitics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit design, maximizing space while minimizing parasitic effects becomes challenging as devices and unit cells shrink, leading to difficulties in designing layouts for improved power, performance, and area (PPA) performance due to uniform transistor sizes and conductive structure inefficiencies.
Innovation Solution
The approach involves forming rows of cells with varying heights and nanoribbon widths, where some rows have a height difference of at least 3 nm, and nanoribbon widths differ by at least 5 nm, allowing for optimized use of gate area and reducing parasitic capacitance by varying transistor device sizes and conductive layer distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform transistor sizes and standard unit cell layouts are used, then manufacturing simplicity is maintained, but parasitic effects increase and space utilization becomes inefficient
Solution Approach 1:
The patent applies local quality by varying transistor device sizes and conductive layer configurations in different regions of the integrated circuit. Specifically, different unit cells contain transistors with different channel widths, and conductive layers are selectively present or absent in different regions, allowing each local area to be optimized for its specific function while reducing overall parasitic effects
Solution Approach 2:
The patent segments the integrated circuit into multiple unit cells with different configurations. Each unit cell is designed independently with specific transistor sizes and conductive layer arrangements, allowing the circuit to be divided into functional blocks that can be optimized separately rather than using a uniform layout throughout
2Area of moving object
If device sizes are reduced to maximize integration density, then area is improved, but parasitic effects become more significant and harder to control
Solution Approach 1:
The patent changes physical parameters of the transistor devices, specifically varying the channel width of transistors in different unit cells. By adjusting this geometric parameter, the design achieves different levels of integration density in different regions while controlling parasitic capacitance, as narrower channels reduce capacitance but increase resistance, requiring balanced parameter selection
3Reliability
If larger transistors are used to reduce parasitic effects, then performance is improved, but available space is reduced and integration density decreases
Solution Approach 1:
The patent applies local quality by assigning different transistor sizes to different unit cells based on their functional requirements. Critical performance paths use larger transistors to reduce parasitic effects and improve speed, while less critical functions use smaller transistors to maximize integration density, achieving overall optimization rather than uniform sizing
4Device complexity
If standard conductive layer distribution is used, then manufacturing complexity is reduced, but gate area utilization becomes inefficient and wasted space increases
Solution Approach 1:
The patent segments the conductive layer structure by selectively including or excluding certain conductive layers in different unit cells. Rather than stacking all conductive layers uniformly throughout the circuit, specific layers are omitted in regions where they are not needed, improving gate area utilization and reducing parasitic capacitance while maintaining manufacturability through systematic layer assignment
Data Source
AI summary
Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.