Stacked Memory Cell Structure for High-Density Semiconductor Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving miniaturization, high integration, high operating speed, favorable electrical characteristics, low power consumption, and large memory capacity while maintaining reliability.
Innovation Solution
A semiconductor device is designed with a stacked structure of memory cells, transistors, and capacitors, utilizing metal oxides and conductive layers to enhance integration, speed, and electrical performance. The device includes a first and second conductor that are electrically connected through an opening in the insulator, allowing for direct contact with the memory cell conductors, thereby reducing the need for additional electrodes and increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase memory capacity, then memory capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertical stacking of memory cells, utilizing the third dimension (height) to increase memory capacity. Multiple memory cells are stacked above a common substrate, with conductors extending vertically to connect to different memory cell layers, thereby achieving higher density without proportionally increasing device complexity.
2Reliability
If additional electrodes are added to connect conductors between memory cells, then electrical connectivity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the function of multiple separate electrodes into a single common substrate that serves as a shared electrical connection point for multiple memory cells. The first and second conductors from different memory cells both connect to the same common substrate, eliminating the need for additional intermediate electrodes and reducing structural complexity while maintaining reliable electrical connectivity.
3Reliability
If more insulator layers are added to isolate conductors in stacked memory cells, then electrical insulation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The second insulator layer serves multiple functions simultaneously: it provides electrical insulation between the first and second memory cells, acts as a structural support layer for the common substrate, and facilitates the formation of openings for conductor connections. This multi-functionality reduces the total number of separate insulator layers needed, thereby lowering manufacturing precision requirements while maintaining adequate electrical insulation.
Data Source
AI summary
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor. The first memory cell and the second memory cell each include a transistor and a capacitor. One of a source and a drain of the transistor is electrically connected to a lower electrode of the capacitor. The first conductor includes a portion in contact with the other of the source and the drain of the transistor included in the first memory cell. A top surface of the first conductor includes a portion in contact with a bottom surface of the second conductor. The second conductor includes a portion in contact with the other of the source and the drain of the transistor included in the second memory cell.