Multi-Step Wafer Stack Trimming for Thin Edge Strength
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Solution Overview
Problem
The thinning of semiconductor wafers for 3DIC fabrication leads to sharp outer edges with low mechanical strength, causing chipping and flaking during processing, and existing edge trimming methods exert stresses that can damage the wafer stack.
Innovation Solution
A multi-step edge trimming process is performed by bonding a second wafer onto a first wafer, followed by sequential edge trimming cuts along the outer edges of the second wafer, and then along the edges of both wafers, using different types of edge trimming cuts to mitigate stresses and reduce damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafers are thinned for 3DIC fabrication, then device density and integration are improved, but mechanical strength decreases causing chipping and flaking
Solution Approach 1:
The edge trimming process is divided into multiple sequential cuts rather than a single cut. The first cut removes a first portion of the outer edge, and the second cut removes a second portion, creating a stepped profile that distributes stress and prevents chipping while maintaining thin wafer dimensions
Solution Approach 2:
Edge trimming is performed as a preliminary action before final wafer stacking and bonding. By pre-shaping the edges and removing vulnerable material beforehand, the wafer is prepared to withstand subsequent processing steps without chipping or flaking
2Strength
If existing edge trimming methods are used, then edge strength is improved, but stresses damage the wafer stack
Solution Approach 1:
The trimming process is segmented into multiple cuts with different orientations and depths. The first cut is made at a first orientation, and the second cut is made at a second orientation different from the first, distributing mechanical stresses across different planes and preventing stress concentration that could damage the wafer stack
Solution Approach 2:
Different portions of the wafer edge receive different treatment through the multi-cut process. The first cut creates a first profile, and the second cut creates a second profile, with each cut optimized for local stress distribution and edge reinforcement without compromising the entire wafer stack
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.