Backside Source-Drain Contact Layout for Smaller IC Cell Heights
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and requires new methodologies for efficient power delivery and contact access in tight spaces.
Innovation Solution
The implementation of backside source or drain contact differentiated access features, which allow for self-aligned access to deeper features while maintaining shallower ones as dummy features, enabling efficient power delivery and reducing interconnect stress through backside power delivery networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node and below
Solution Approach 1:
The patent applies backside contact formation instead of conventional frontside contact formation. By accessing source/drain regions from the backside of the substrate, the invention enables precise alignment and contact formation at 10nm node and below, overcoming the limitations of frontside processes while managing fabrication complexity through inverted process flow.
Solution Approach 2:
The patent transitions from two-dimensional frontside contact formation to three-dimensional backside access. By utilizing the vertical dimension and accessing contacts from the substrate backside, the invention achieves improved precision for scaled features without proportionally increasing process complexity.
2Power
If front side power delivery is used, then power delivery is achieved, but device complexity increases due to wide power metal wires requirement
Solution Approach 1:
The patent implements backside power delivery by forming power contacts and interconnects on the substrate backside rather than frontside. This inversion eliminates the need for wide power metal wires on the frontside, reducing interconnect structure complexity while maintaining effective power delivery through the substrate.
Solution Approach 2:
The patent moves power delivery infrastructure from the frontside plane to the backside plane, utilizing the third dimension (substrate thickness) to route power interconnects. This dimensional transition reduces frontside complexity while preserving power delivery functionality.
3Volume of moving object
If cell height is reduced for compactness, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
By forming contacts from the backside, the invention achieves self-aligned contact formation that maintains precision even with reduced cell heights. The backside access methodology inherently provides alignment references that preserve manufacturing precision despite compact vertical dimensions.
4Quantity of substance
If multi-gate transistors are scaled down, then device density increases, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The backside contact formation methodology provides improved dimensional control for scaled multi-gate transistors. By accessing contacts from the backside, the process reduces variability in feature dimensions and improves precision, enabling higher device density without sacrificing manufacturing control.
Data Source
AI summary
Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.