3D Memory Stack Interconnects for Higher Bit Density
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Solution Overview
Problem
Existing 3D NAND flash memory architectures face limitations in reducing the area of peripheral circuitry, leading to high cost per bit and limited bit density, despite advancements in stacking layers.
Innovation Solution
Implement a 3D heterogeneously interconnected memory system with feature logic and memory logic circuitry interconnected through various techniques, including Through-Array Vias, Through-Array Contacts, and direct bonding, to enhance communication and reduce peripheral circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND array stacking layers are increased, then bit density is improved, but peripheral circuit area reduction is limited
Solution Approach 1:
The memory system is divided into multiple stacked dice (first die, second die, third die) with distinct functional allocations. The first die contains memory strings and memory logic circuitry, the second die contains feature logic circuitry, and the third die contains additional memory logic. This segmentation allows peripheral circuit functions to be distributed across multiple layers rather than confined to a single plane, effectively reducing the footprint of peripheral circuits while maintaining high bit density through vertical stacking.
Solution Approach 2:
The patent transitions from traditional 2D peripheral circuit layout to 3D vertical stacking architecture. By placing peripheral circuitry (memory logic and feature logic) in separate stacked dice rather than surrounding the memory array in the same plane, the design utilizes the vertical dimension to reduce peripheral circuit area occupation. Through-array vias and inter-die connections enable communication between stacked layers, achieving high integration without increasing planar footprint.
2Area of stationary object
If CuA technology is used to place peripheral circuits under 3D NAND array, then chip size is reduced, but peripheral circuit area reduction is limited
Solution Approach 1:
The system segments peripheral circuit functions into separate stacked dice rather than integrating them under the array in the same die. Memory logic circuitry is placed on the first die with memory strings, feature logic on the second die, and additional memory logic on the third die. This segmentation enables more aggressive area reduction by utilizing vertical stacking space, achieving better cost per bit through higher effective density without the area limitations of CuA technology.
Solution Approach 2:
The patent implements a nested structure where multiple functional dice are stacked and interconnected. The first die with memory strings contains memory logic circuitry, which is further nested with feature logic circuitry on the second die and additional memory logic on the third die. This nested arrangement allows peripheral circuits to be embedded within the vertical stack rather than occupying peripheral areas, achieving superior area reduction compared to CuA technology.
3Productivity
If logic circuits are integrated in stacked dice, then system-level performance is improved, but device complexity increases
Solution Approach 1:
Through-array vias serve as intermediary connection structures enabling communication between stacked dice. The vias penetrate through the array die to establish electrical connections between memory logic circuitry on the first die, feature logic circuitry on the second die, and additional memory logic on the third die. This intermediary connection mechanism simplifies the overall interconnection architecture compared to alternative approaches requiring complex back-side routing or wire-bonding, thereby managing device complexity while achieving high system-level performance.
Data Source
AI summary
A 3D heterogeneously interconnected memory provides improved performance as well as reduced cost for non-volatile memory. A plurality of interconnection techniques is used to interconnect a plurality of dice using 3D stacking of the dice. One of the dice implements an array of memory strings to provide non-volatile storage. Another one of the dice implements logic circuits to improve performance and/or reduce cost associated with implementing a memory component using the array of memory strings. Example interconnection techniques use direct bonding, through-array vias, through-array contacts, and/or through-silicon vias.