3D Ferroelectric Memory Cell Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the minimum feature size of semiconductor devices while addressing issues such as parasitic capacitance and energy consumption, particularly in three-dimensional memory devices.
Innovation Solution
The development of a three-dimensional memory device with ferroelectric material, where a method involves forming layer stacks with dielectric, channel, and source/drain layers, lining openings with ferroelectric material, and forming gate electrodes to enhance memory cell efficiency and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but parasitic capacitance increases and energy consumption rises
Solution Approach 1:
The patent applies local quality by using ferroelectric material specifically in the tunnel barrier region of the memory device, rather than uniformly across the entire device. This localized application of functional material optimizes the specific region where charge trapping occurs, improving memory cell efficiency while minimizing overall parasitic capacitance. The ferroelectric layer is precisely positioned at the semiconductor-dielectric interface where it provides maximum benefit for charge storage.
Solution Approach 2:
The patent employs composite materials by combining ferroelectric material with traditional semiconductor and dielectric layers. This creates a multi-layer structure where the ferroelectric component provides enhanced charge trapping capability, while the surrounding dielectric and semiconductor layers maintain device functionality. The composite structure allows for reduced feature sizes without proportionally increasing parasitic capacitance, as the ferroelectric material provides higher charge density per unit volume.
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but parasitic capacitance increases
Solution Approach 1:
The patent changes the electrical parameters of the tunnel barrier by introducing ferroelectric material, which has high dielectric constant and ferroelectric polarization properties. This parameter change allows for stronger electric field confinement and more efficient charge trapping in the tunnel region. The ferroelectric material's spontaneous polarization creates an internal electric field that enhances charge retention, thereby reducing the need for larger device dimensions and associated parasitic capacitance.
Solution Approach 2:
The patent replaces traditional charge storage mechanisms that rely on physical device size with a ferroelectric-based mechanism that uses material properties for charge trapping. Instead of increasing physical dimensions to store more charge (which would increase parasitic capacitance), the invention uses the ferroelectric material's polarization properties to achieve higher charge density in a compact volume, effectively substituting a material-property-based system for a geometry-based system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the integration of high-density memory arrays with reduced parasitic capacitance and energy consumption, allowing for smaller, cheaper, and faster semiconductor devices.
Implementation Method 1
lining sidewalls of the openings with a ferroelectric material
Data Source
AI summary
A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.