Semiconductor Boundary Structure for Mixed-Voltage Isolation

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Solution Overview

Problem

In semiconductor manufacturing, the transition between middle/high voltage and low voltage device regions with different precision nano-processes leads to structural issues and increased costs due to mismatched device sizes and precision, resulting in yield decline and mutual interference between regions.

Innovation Solution

A semiconductor structure featuring a protruding part or sharp corner defined by a deep trench and a shallow trench at the boundary between middle/high voltage and low voltage device regions, acting as a buffer to prevent mutual influence, with the top surface of the protruding part aligned with the surrounding region's flat top surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If different precision nano-processes are used for middle/high voltage and low voltage device regions, then device precision and adaptability are improved, but structural problems occur at region boundaries and manufacturing complexity increases

Engineering Contradiction:
Improvedevice precisionVSAvoidboundary structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The boundary region is segmented into multiple sub-regions (first boundary sub-region with deep trench, second boundary sub-region with shallow trench) to separately address the isolation needs of different voltage regions. This segmentation allows each sub-region to be optimized independently for its specific function, resolving the structural complexity at the boundary while maintaining high precision in both device regions.

Inventive Principle:
Principle #1Segmentation

2Productivity

If device size does not match nano-process precision, then cost increases and yield declines, but using different nano-processes for different regions creates boundary structural problems

Engineering Contradiction:
Improvedevice yieldVSAvoidboundary structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Different boundary structures (deep trench vs. shallow trench) are applied to different local regions based on their specific isolation requirements. The first boundary sub-region uses a deep trench structure optimized for isolating middle/high voltage devices, while the second boundary sub-region uses a shallow trench structure suitable for low voltage devices. This local optimization allows each region to achieve its required precision and yield without forcing a uniform complex structure across the entire boundary.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If middle/high voltage and low voltage device regions are placed on the same chip, then chip functionality and adaptability are improved, but mutual interference occurs between regions

Engineering Contradiction:
Improvechip functionalityVSAvoidmutual interference between regions
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The boundary structure acts as an intermediary between the middle/high voltage device region and the low voltage device region. The deep trench and shallow trench structures serve as isolation barriers that mediate the interaction between the two voltage regions, preventing direct electrical interference while allowing both regions to coexist on the same chip. This intermediary structure enables the chip to maintain high adaptability and functionality without suffering from mutual interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250015186A1Semiconductor structure
Publication Date: 2025.01.09 UNITED MICROELECTRONICS CORP
  • US20250015186A1 patent drawing
  • US20250015186A1 patent drawing
  • US20250015186A1 patent drawing

AI summary

The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.