ELAIC Chip Tiling for Dense Interconnect and Thermal Dissipation
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Solution Overview
Problem
The microelectronics industry faces challenges in integrating multiple processor and accelerator chips with minimal chip-to-chip spacing to minimize interconnect length, achieve higher bandwidth connections, and manage thermal dissipation while optimizing for size, weight, and power (SWaP), as traditional approaches like wafer level packaging face limitations in reliability and chip package interaction.
Innovation Solution
The development of Extremely Large Area Integrated Circuits (ELAIC) that combine multiple heterogeneous dies into a single package through chip tiling, using build-up layers and close-packed assembly with 0-20 μm separation, incorporating plated metal for heat-sink functionality, and precise alignment techniques to achieve high-density, efficient heat-dissipation and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple chips are integrated with minimal chip-to-chip spacing to reduce interconnect length, then bandwidth connection is improved, but thermal dissipation becomes more difficult to manage
Solution Approach 1:
The patent transitions from traditional 2D planar integration to 3D stacked integration using wafer-level packaging with through-silicon vias (TSVs). Multiple chips are vertically stacked and interconnected through the substrate thickness, enabling minimal horizontal spacing while managing thermal paths in the vertical dimension. This dimensional change allows high bandwidth connections through short interconnects while providing dedicated thermal vias and heat dissipation paths through the substrate.
Solution Approach 2:
The patent introduces an intermediary substrate layer with integrated TSVs and thermal management structures that mediates between the closely spaced chips. This substrate acts as a thermal highway, providing separate pathways for signal interconnection and thermal dissipation, allowing chips to be positioned with minimal spacing for high bandwidth while thermal energy is efficiently conducted away through the intermediary substrate structure.
2Productivity
If wafer level packaging is used to achieve high functionality in smaller packages, then integration density is improved, but reliability and chip package interaction challenges increase
Solution Approach 1:
The patent changes critical packaging parameters by transitioning from chip-level to wafer-level integration, and from surface-mount to through-substrate interconnections. The use of TSVs changes the interconnect geometry from lateral to vertical, reducing interconnect length and inductance. These parameter changes enable higher integration density while improving reliability by reducing the number of external package interfaces and minimizing chip package interaction challenges.
Solution Approach 2:
The patent employs composite material structures in the wafer-level package, combining silicon substrates with copper TSVs, low-k dielectric materials, and thermal interface materials. This composite approach allows simultaneous optimization of electrical interconnection, thermal management, and mechanical reliability, achieving high integration density while maintaining robust chip package interaction reliability.
3Quantity of substance
If traditional wiring density approaches are used (reducing via dimensions, increasing wiring layers), then wiring density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent resolves the wiring density vs. fabrication complexity contradiction by moving interconnections to the vertical dimension through TSVs. Instead of increasing the number of lateral wiring layers (which increases fabrication complexity), the design uses vertical through-silicon vias to achieve high interconnect density. This dimensional change provides high wiring density with relatively simple fabrication processes, as TSVs can be formed using standard semiconductor manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
ELAICs enable systems to perform like a single heterogeneous chip with reduced latency and increased efficiency, providing up to 99% Si content, minimal gap fill, and efficient thermal management, addressing the limitations of traditional integration methods.
Implementation Method 1
Include plated metal (e.g., Cu) and/or alloy based inter-chip gap fill to create a built-in heat-sink for efficient heat-dissipation
Data Source
AI summary
Extremely Large Area Integrated Circuits (ELAIC) may become an attractive tiling method for 2D integration to meet the demands of higher functionality in ever smaller packages, especially when coupled with the use of heterogeneous chips. This new tiling solution is suitable for combining multiple memory, ASICs, CPU, GPU, etc., into a single package. This approach also favors system integration with high density power delivery by appropriate build-up materials, design and thermal management. ELAIC technology with bare multi-die integration offers a number of advantages relative to the equivalent integration methods.