PD-SOI Transistor Body-Source Coupling to Eliminate Kink Effect
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Solution Overview
Problem
PD-SOI transistors suffer from a kink effect due to hole accumulation in the channel, leading to reduced threshold voltage and undesirable properties in SRAMs, such as reduced static noise margin and increased variability, while body contact solutions increase die area and routing complexity.
Innovation Solution
Implementing an enhanced body-to-source (EBTS) architecture in PD-SOI transistors, where a heavily doped region forms an ohmic contact to the body and couples through a silicide layer to the source, allowing hole conduction from the channel to the source contact, thus eliminating the need for a separate body terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate body terminal is added to PD-SOI transistors to eliminate the kink effect, then the threshold voltage stability is improved, but the device complexity and die area increase
Solution Approach 1:
The patent merges the body contact function with the source contact by forming an ohmic contact between the heavily doped source region and the body. This integration eliminates the need for a separate body terminal while maintaining the ability to remove accumulated holes from the channel, thus resolving the contradiction between reliability improvement and device complexity reduction
Solution Approach 2:
The source contact is designed to serve dual functions: as the electrical connection for the source terminal and as the body contact. This multi-functionality allows the same structure to perform both source current conduction and body potential control, eliminating the need for additional body terminal infrastructure
2Reliability
If a separate body terminal is added to PD-SOI transistors to eliminate the kink effect, then the threshold voltage stability is improved, but the routing complexity increases
Solution Approach 1:
By combining the body contact and source contact into a single ohmic contact structure, the patent eliminates the need for separate routing paths for body and source connections. This reduces routing complexity while maintaining the reliability benefits of body contact
3Reliability
If body contact is implemented in PD-SOI transistors, then the kink effect is reduced, but the die area increases
Solution Approach 1:
The patent integrates the body contact function within the existing source contact structure, eliminating the need for additional die area that would be required for a separate body terminal and its associated contact hole and metal routing
4Ease of manufacture
If PD-SOI transistors are used instead of FD-SOI, then the manufacturing cost is reduced, but the kink effect increases
Solution Approach 1:
The heavily doped source region acts as an intermediary that facilitates hole removal from the channel through the ohmic contact to the source terminal. This intermediate structure enables PD-SOI transistors to achieve kink effect reduction without requiring the more complex FD-SOI depletion structure
Solution Approach 2:
The patent modifies the doping parameters of the source region, making it heavily doped to create an ohmic contact with the body. This parameter change enables the source contact to function as a body contact, allowing PD-SOI transistors to achieve improved threshold voltage stability while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The EBTS architecture effectively addresses the kink effect, reducing die space requirements and routing complexity, enabling high-density SRAM bitcells without well-defined source and drain transistors.
Implementation Method 1
a first doped region doped with the first dopant type, wherein the first doped region is doped more heavily than the first body and has a first ohmic contact to the first body
Data Source
AI summary
A partially depleted silicon-on-insulator circuit is provided that includes a first transistor having a well-defined source and drain and a second transistor not having a well-defined source or drain. A doped region forms an ohmic contact to a body of the first transistor and the second transistor. Should the first transistor and the second transistor each comprises an NMOS transistor, a silicide layer couples the doped region to the source contact of the first transistor. Conversely, a silicide layer couples the doped region to a drain contact of the first transistor if the first transistor and the second transistor each comprise a PMOS transistor.


