Stacked Transistor S/D Contact Structure With Enlarged Bottom Contact Area
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Solution Overview
Problem
In stacked transistor structures, the access to the bottom transistor is partially blocked by the top transistor, resulting in smaller un-blocked contact areas and higher resistance due to the shrinking size of semiconductor devices as they move to smaller nodes.
Innovation Solution
A semiconductor structure is formed with a first transistor on a substrate and a second transistor on top of the first transistor, featuring a source/drain (S/D) contact with both horizontal and vertical portions. The horizontal portion extends from the sidewall of the vertical portion, and a portion of the horizontal portion is vertically between the S/D regions of the first and second transistors. This configuration allows for an enlarged contact area with the bottom transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked transistor structure is used to increase device density, then productivity is improved, but the contact area to the bottom transistor decreases resulting in higher resistance
Solution Approach 1:
The S/D contact is extended from a simple vertical configuration to include a horizontal portion that runs laterally between the first and second S/D regions. This dimensional extension allows the contact to access the bottom transistor through the space created by the offset arrangement, effectively adding a lateral pathway that bypasses the blocking effect of the top transistor.
Solution Approach 2:
The S/D contact structure is nested within the three-dimensional space created by the offset stacked transistor arrangement. The horizontal portion of the contact is positioned in the vertical space between the first and second S/D regions, utilizing the volumetric space efficiently to achieve contact with the bottom transistor without requiring additional lateral space.
2Productivity
If device sizes are shrunk to smaller nodes to increase integration, then productivity is improved, but contact area shrinks resulting in higher resistance
Solution Approach 1:
Instead of increasing contact area in the lateral plane (which is constrained by shrinking device sizes), the invention extends the contact into the vertical dimension by adding a horizontal portion that utilizes the vertical space between stacked S/D regions. This allows contact area expansion without increasing lateral footprint.
Solution Approach 2:
The S/D contact is segmented into distinct vertical and horizontal portions, each serving a specific function. The vertical portion provides direct access to the bottom transistor, while the horizontal portion extends laterally to increase contact area with the first S/D region, allowing the contact structure to optimize area utilization in three-dimensional space.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor on a substrate; a second transistor on top of the first transistor; and a source/drain (S/D) contact contacting a first S/D region of the first transistor, where the S/D contact has a horizontal portion and a vertical portion, the horizontal portion extending from a sidewall of the vertical portion and a portion of the horizontal portion being vertically between the first S/D region of the first transistor and a second S/D region of the second transistor. A method of forming the same is also provided.