Array Substrate Layout With Merged Masking and Via Etching
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Solution Overview
Problem
Existing array substrate fabrication processes for displays are complicated due to the need for multiple masking processes to form light shielding parts, sources, drains, and gates, leading to inefficiencies and potential signal interference issues.
Innovation Solution
The array substrate design integrates the light shielding part, source, and drain on the same layer, with the gate, source landing electrode, and drain landing electrode on the same layer, allowing for reduced masking processes and improved contact precision through via holes etched simultaneously, using dry etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking processes are used to form light shielding parts, sources, drains, and gates separately, then each component can be precisely formed, but the fabrication process becomes complicated and time-consuming
Solution Approach 1:
The patent combines the formation of light shielding parts, sources, and drains into a single masking process by integrating them onto the same layer. This merging approach reduces the number of separate masking processes required while maintaining the precision of component formation, directly addressing the contradiction between manufacturing precision and fabrication complexity
2Manufacturing precision
If multiple masking processes are used for fabricating different components, then each component can be independently optimized, but the fabrication time and production efficiency decrease
Solution Approach 1:
By merging light shielding parts, sources, and drains onto the same layer and forming them in a single masking process, the patent significantly reduces fabrication time and improves productivity while still allowing for independent optimization of each component's design and positioning
3Manufacturing precision
If via holes are etched separately for different connections, then contact precision can be optimized, but signal interference increases and fabrication reliability decreases
Solution Approach 1:
The patent merges the etching processes for via holes by etching them simultaneously in a single process step. This approach maintains contact precision while reducing signal interference between separately etched via holes and improving fabrication reliability through process consistency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This simplifies the fabrication process, enhances contact reliability, and reduces signal interference by optimizing the layout and etching methods, thereby improving the efficiency and quality of the array substrate.
Implementation Method 1
via holes etched simultaneously, using dry etching
Data Source
AI summary
An array substrate, a display device and a fabrication method are provided. The array substrate includes a first metal layer at one side of a base substrate, the first metal layer including a light shielding part, a source, a drain in a display area; a second metal layer at a side, facing away from an active layer, of gate insulating layer, the second metal layer includes a gate, a source-landing electrode a drain-landing electrode in the display area, the source-landing electrode is in contact with the active layer and the source through a first via hole penetrating through the gate insulating layer and a buffer layer and exposing one end of the active layer, the drain-landing electrode is in contact with the active layer and the drain through a second via hole penetrating through the gate insulating layer and the buffer layer and exposing other end of the active layer.