Shared-Electrode Memory Cell Layout for Dense Reliable Arrays
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Solution Overview
Problem
Current semiconductor devices and memory devices face challenges in achieving high integration, high operating speed, excellent electrical characteristics, low power consumption, and large memory capacity while maintaining reliability and minimizing variations in transistor electrical characteristics.
Innovation Solution
A memory device is designed with a specific configuration including multiple transistors and capacitors, where a shared electrode acts as a protective film, covering the memory cell array to reduce noise and enhance reliability. This configuration allows for efficient integration and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices are scaled down to increase integration density, then memory capacity and area efficiency improve, but transistor electrical characteristics vary and reliability deteriorates
Solution Approach 1:
The patent changes the physical and chemical parameters of the semiconductor layer by using specific material compositions (In-Ga-Zn-O with controlled atomic ratios) and deposition conditions to achieve consistent transistor characteristics despite scaling. The semiconductor layer is formed with precise control over composition and structure to maintain electrical performance at smaller dimensions
Solution Approach 2:
The patent applies local quality by creating specific structural features at critical locations, such as the stacked transistor configuration where each transistor layer has optimized dimensions and the semiconductor layers are positioned to ensure uniform electrical characteristics across the device stack, compensating for scaling effects
2Area of stationary object
If transistor dimensions are reduced to increase integration, then area efficiency improves, but operating speed decreases
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional stacked transistors, stacking multiple transistor layers vertically. This dimensional change allows maintaining larger effective channel area for higher operating speed while occupying smaller footprint area, thus resolving the contradiction between area efficiency and operating speed
3Use of energy by moving object
If power consumption is reduced for portable devices, then energy efficiency improves, but operating speed and performance deteriorate
Solution Approach 1:
The patent utilizes the high field-effect mobility inherent in In-Ga-Zn-O semiconductor materials to achieve fast switching speeds at lower operating voltages. By controlling the semiconductor layer composition and structure, the device can operate at reduced power levels while maintaining high operating speed through optimized electrical characteristics
Data Source
AI summary
A memory device that can be scaled down or highly integrated is provided. The memory device includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode and a second electrode. The second capacitor includes the first electrode and a third electrode. One of a source and a drain of the first transistor is electrically connected to the second electrode. One of a source and a drain of the second transistor is electrically connected to the third electrode. A gate of the third transistor is electrically connected to the second electrode. The first electrode includes a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor, and is supplied with a fixed potential or a ground potential.