3D CMOS Channel Stacking With Silicide Interconnects
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistors to single-digit nanometer nodes, particularly in achieving high transistor density in planar devices, and struggle with the complexity of implementing 3D integration for logic chips beyond flash memory applications.
Innovation Solution
A method for fabricating 3D semiconductor apparatuses involves forming a multilayer stack of selectively etchable dielectric materials, creating vertical channels, and coupling them with silicide to enable 360-degree access for optimal routing, allowing for the formation of vertically stacked CMOS devices with reduced layout and enhanced scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar scaling is continued to increase transistor density, then transistor density per unit area improves, but manufacturing complexity and process control difficulty worsen at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional planar transistor scaling to three-dimensional vertical stacking. Multiple transistor layers are stacked vertically with intermediate transfer layers enabling electrical connections between layers. This dimensional change allows continued transistor density improvement without the same degree of manufacturing complexity increase, as the vertical architecture provides new routing and connection approaches.
2Quantity of substance
If 3D vertical stacking is implemented to increase transistor density, then transistor density in volume improves, but device structure and interconnection complexity worsens
Solution Approach 1:
The patent segments the 3D structure into distinct transistor layers separated by intermediate transfer layers. Each layer can be independently formed and controlled, with the transfer layers providing modular connection points. This segmentation reduces interconnection complexity by breaking down the monolithic 3D structure into manageable, repeatable units that can be systematically interconnected.
Solution Approach 2:
The patent introduces intermediate transfer layers as mediators between vertically stacked transistor layers. These transfer layers provide the interface and connection mechanism between layers, simplifying the interconnection process by providing dedicated intermediary structures rather than requiring direct complex routing between all layers. The transfer layers act as buffer zones that manage the electrical and structural transitions between layers.
3Quantity of substance
If transistor size is reduced to increase density, then transistor density improves, but manufacturing precision and process control requirements worsen
Solution Approach 1:
By moving to vertical stacking, the patent achieves density improvement through the third dimension rather than continued lateral miniaturization. This allows transistor dimensions in the plane to be larger while still achieving high density through vertical multiplication. The process control precision requirements are reduced compared to single-digit nanometer planar scaling, as the vertical architecture provides manufacturing latitude.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significant device scaling and efficient 3D integration of CMOS transistors, providing optimal routing and increased transistor density, which addresses the limitations of planar devices and simplifies the fabrication of complex logic chip designs.
Implementation Method 1
forming a silicide at the uncovered portion to couple the first channel to the second channel
Implementation Method 2
a plurality of layers of at least three different dielectric materials that are capable of being etched selectively with respect to one another
Data Source
AI summary
Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.