Solid-State Devices TRIZ Cases

Bonding pixel and logic wafers before thinning cuts connection-hole aspect ratio, simplifies processing, and lowers image sensor cost.

Separated source structures and a filling pattern stabilize 3D memory stacking by preventing sacrificial layer removal and oxidation.

A three-sub-pixel via layout exposes electrode, power-line, and floating regions to enlarge emission area and improve light emission efficiency.

A stacked NMOS clamp with feedback-triggered gate bias lowers ESD trigger voltage, reduces GIDL, and helps prevent latch-up in ICs.

A monolithic InGaN/GaN pixel stack generates RGB light directly, avoiding pick-and-place assembly, conversion losses, and unstable InGaAlP red emission.

Block-based first and second pixel readout enables area-specific exposure during capture, improving full-frame display image generation.

Trench portions in the display bank reduce step height and residue contact, preventing contact electrode breakage and short circuits.

A feedback strobe monitoring circuit checks read strobe duty ratio through existing pads, enabling efficient testing in stacked memory.

Overlapping data lines and trunk electrodes widen VA LCD viewing angles while preserving aperture, transmittance, and lower energy use.

A 3D core-shell LED uses sidewall active layers, transparent electrodes, and passivation to raise luminance and efficiency in compact displays.

An in-molded barrier film on the cover window blocks gas during high-temperature testing, preventing display-panel bubbles and extra assembly steps.

A transparent elastomer and vacuum hot pressing strengthen LED layer bonding, reducing cracks under bending and heat cycles.

Non-uniform data-line and connecting-member geometry improves photolithography accuracy, pixel repair space, and leakage control.

Asymmetric aperture spacing pre-compensates reflective sheet heat shrinkage to preserve LED luminance uniformity over time.

A transistor gate extending into the substrate frees lateral pixel area for photodiodes, boosting fill factor and quantum efficiency.

An internal conductive structure bridges touch leads to metal wiring across stacked film layers, avoiding flexible boards and easing panel fabrication.

A metal layer and offset hole layout shield bypass lines from external light while preserving transmission area performance for integrated sensors and cameras.

Peripheral gaps and convex transmissive bodies redirect side and top light to raise brightness and cut power use in LED modules.

A void and intermediary semiconductor pattern relieve strain and lattice mismatch in long-wavelength display emitters, cutting internal defects.

A planar epitaxial SPAD structure replaces deep trench formation to avoid oxide pilling, cut dark current defects, and improve detection probability.

A hollow or low-k channel core in NAND memory strings reduces adjacent-cell interference and preserves performance at tighter layer pitch.

A trench and dicing layout preserves first semiconductor layers to pack LED units more densely, cut stack waste, and avoid short circuits.

Dummy through-array vias improve channel-to-conductor coupling in 3D NAND stair-step blocks, reducing defects and electric field effects.

Low-transmittance optical layers placed between light-emitting devices absorb stray light to cut reflection, crosstalk, and uneven emission.

Dummy pixel areas and electrode lines outside the active display keep electrode spacing aligned, reducing pixel performance variation.

Openings formed at threading dislocations let active-layer light exit without crossing defect paths, reducing loss and preserving intensity.

A shared blue emission layer with current injection limiting and color conversion improves micro-LED color purity and light efficiency while easing transfer.

A piezoelectric switch replaces semiconductor TFT action to improve display switching stability and achieve a true off state with lower leakage.

Adjacent ESD diodes use N-well collector guard bands to shrink IO pad cell area, lower series resistance, and reduce latch-up risk.

A dummy portion, multi-directional tensioning, pressing, and laser fixing reduce mask deformation while improving display mask alignment.

Annealing-driven aluminum diffusion shapes a zirconium aluminum oxide capacitor dielectric to lower leakage current and strengthen breakdown voltage.

Level differences in stacked narrow band filters and interlayer films curb multiple reflections and suppress spectral ripple in imaging sensors.

Embedded optical nanostructures transform incident light before grating coupling, simplifying wafer-level alignment and reducing component count.

Orthogonal drain contact hole geometry blocks black-state light leakage in LCD pixels while preserving source connection reliability.

A grooved auxiliary electrode lets the cathode extend into the non-pixel region, improving voltage uniformity and avoiding OLED layer adhesion.

Multiple electrodes on both sides of an organic photoelectric film enable adjustable pixel-area charge readout for more accurate focus detection.

A split photosensitive and photo-insensitive pixel layout improves phase difference autofocus accuracy while allowing simultaneous light incidence.

Separate resistive layers let memory cells and conductive vias be tuned independently, improving efficiency and current-stress protection.

Separating 3D memory arrays from non-memory logic across two dice boosts computational density and bandwidth for non-arithmetic processing.

Actuated RGB LED arrays shift in x-y to vary overlap and packing, balancing brightness, color gamut, and resolution.

Silicide links vertically stacked CMOS channels to raise transistor density while easing routing and planar scaling limits.

An overlap adhesive layer at the polarizer edge bonds the protective layer in the bending area to prevent delamination and reduce display dead space.

Staggered common electrode lines raise LCD transmittance and reduce color shift while avoiding transparent-electrode overlap in non-display areas.

Extension and dummy lines balance coupling capacitance and cancel external noise in multi-region sensor panel wiring for accurate position detection.

Through-hole-filled opposing spacers strengthen fine-pixel LCD panels while reducing electrode unevenness, light leakage, and color non-uniformity.

A cascode source follower uses capacitive voltage division to isolate supply noise, improving PSRR and SNR without complex filtering.

Shared light transmission patterns and column spacers simplify OLED color conversion layers while improving light conversion and display quality.

Insulating line patterns split a 3D memory stack to raise density while preserving connection regions and device reliability.

Selective current through one field line writes magnetic bits reliably while cutting power use and avoiding saturation in the magnetic circuit.

A high-k third insulating layer and radical oxidation reduce electric-field leakage while preserving 3D NAND integration and oxide stability.

Conformal word lines and buried bit lines resolve gate length control challenges in vertical semiconductor memory devices.

Flow guiding grooves direct alignment layer liquid solution away from conductive connection lines, preventing accumulation at fan out area acute portions.

Multiplexes OLED cathodes as pressure induction electrodes to integrate force touch sensing within the display stack.

A semiconductor chip integrates a lateral conductive layer to withstand high operating currents without damaging the thin contact interface.

Segmented doping in a semiconductor pick-up region stabilizes voltage supply, reducing misalignment defects and improving manufacturing yield.

A lightly doped breakdown protection region interrupts charge carrier paths to reduce pinning potential and electric field stress at isolation walls.

Piezoresistive sensors measure strain in flexible panels, enabling controllers to adjust operations and extend lifespan.

Segmented first electrode with high resistance regions prevents leakage current from short defects, maintaining OLED reliability.

Gate electrode and isolation film act as masks to form LDD regions, eliminating photolithography steps that increase manufacturing costs.

Targeted etching exposes scribe lines before wafer dicing, preventing micro-cracks and delamination in optical fingerprint sensors.

A composite grid structure with reflective layers minimizes optical crosstalk in CMOS image sensors.

A second carrier blocking layer in a quantum dot light-emitting diode balances electron and hole injection rates, reducing heat loss from unbalanced carriers.

A pixel-level black matrix layer integrates with an elliptical polarizer to enhance emissive efficiency in display panels.

Flip-chip modular tiles eliminate wire bonds to reduce parasitics and accelerate development time.

A termination controller detects signal line loading to manage data transmission in multi-chip packages.

Segmented adhesive layers with moisture-absorbent fillers protect organic electronic diodes from humidity without direct contact.

A deep level impurity region creates an extra tunneling path at the metal-semiconductor interface to lower contact resistivity in scaled devices.

Auxiliary wiring segments enable electrical discharge to remove organic layers, forming low resistance connections for OLED upper electrodes.

Laser-induced dark spots in a white sub-pixel enable defect repair through color compensation, maintaining display quality.

A first light-emitting layer decomposes metal compounds in the bezel area to prevent short circuits between signal lines.

Reducing second-conductivity impurity in the SiC guard ring surface layer disperses current density to prevent device destruction during avalanche breakdown.

Support structures prevent gate electrode leaning and improve overlay accuracy during fin cut processes in ten nanometer semiconductor devices.

A folded substrate structure uses a filling member between terminal regions and rear surfaces to maintain structural integrity.

A titanium nitride orientation layer controls crystal alignment in ferroelectric capacitors.

A semiconductor light emitting device applies a convex lens structure to resolve the trade-off between compact chip size and light extraction efficiency.

Segmented molybdenum reflection structures provide complete laser coverage to resolve incomplete sintering in narrow-bezel OLED manufacturing.

Segmented isolation structures with reflective etched layers reduce pixel crosstalk while lowering fabrication costs.

A planar lens structure with alternating insulating parts refracts light to enhance pixel signal quality in photoelectric conversion apparatuses.

Mesoporous acrylamide polymer enables efficient fluorescence emission in solid state through dense arylene group stacking.

Incorporates inclined electrode portions to redirect light emission, reducing internal reflection and improving color reproducibility across viewing angles.

A stress buffer layer prevents substrate warpage during deposition of stacked insulating layers, maintaining flatness for reliable vertical channel formation.

A semiconductor memory device uses a staircase structure with variable electrode film thickness to enable high integration density.

An oxygen-supplying layer stabilizes resistance switching in non-precious metal electrodes by regulating oxygen ion migration.

Connecting the light-reflecting layer to the substrate prevents charging damage to the photoelectric conversion unit during manufacturing.

Stacked substrates with intersecting crystal planes reduce warpage and stress in three-dimensional semiconductor devices.

Read out integrated circuit merges phase-change material switches with test circuitry to generate conductivity skew data.

Introducing a diffusion barrier layer prevents oxygen exchange at the electrode interface, resolving integration difficulties with reactive materials.

Thermally conductive material between phase change memory cells dissipates heat to reduce thermal crosstalk and prevent unintended resistance changes.

Lower auxiliary wiring connects to the OLED cathode between the anode and planarization layer, reducing voltage drop without shrinking the light-emitting area.

Controlled sol gel spinning, drying, and oxidizing baking remove organic residue to prevent radial edge spikes in piezoelectric thin films.

A correlated electron switch fabric uses Mott transitions to enable abrupt impedance switching between conductive and insulative states.

Introducing an air gap under passive devices reduces parasitic shunt capacitance, enhancing tuning range and quality factor.

Segmented finger like arms reduce electrical resistance and prevent moiré interference in illumination devices.

An organic electroluminescent display adjusts optical path lengths to reduce drive voltage while maintaining high luminous efficiency.

A light emitting device package lens with a recessed area and curved surface optimizes viewing angle and luminous intensity distribution.

An intermediate refractive index layer reduces total reflection loss at interfaces, improving luminance and lifespan in organic electroluminescence elements.

Vertical wiring routing above the common electrode resolves the contradiction between touch sensing functionality and pixel aperture ratio.

Dual-layer conductive film structures simultaneously pattern gate electrodes and pixel electrodes in liquid crystal display fabrication.

A multilayer sealing film uses a buffer layer to distribute shear stress and prevent delamination in organic EL displays.

Varying epitaxial growth thickness on inner versus outer fin surfaces reduces gate contact shorting risks while maintaining low series resistance.

Stripping a sacrificial layer removes organic overflow, resolving slope climbing and uneven thickness in OLED thin film encapsulation.

A light emitting device uses narrow emission spectrum phosphors to adjust chromaticity and enhance color reproducibility.

Segmented bi-layer stacks with specific refractive index ratios eliminate alignment errors and surface roughness during multilevel fabrication.

Halide perovskite combined with transparent electrodes achieves high color purity and double-sided emission, resolving low purity issues in organic displays.

Zigzag region separation patterns disperse light to reduce crosstalk and noise differences between adjacent pixels in high-resolution CMOS image sensors.

A light-emitting device uses organic compounds with bicarbazole and heteroaromatic ring skeletons to enhance thermal stability.

Segmented buried gates obliquely cross active regions to prevent voltage interference and enhance integration density.

A ferroelectric memory device uses κ-aluminum oxide doped with magnesium, silicon, hafnium, tungsten, or ruthenium to enhance coercive electric field strength.

Integrating a resistive memory component with a selector via shared active material reduces circuit complexity while maintaining reliable switching performance.

Segmented RRAM cells with isolation transistors suppress sneak currents, resolving manufacturing precision and operation stability trade-offs.

Dummy MTJ arrays maintain thermal stability during solder reflow, protecting trim codes from disruption.

Dynamic bias voltage switching isolates signal photocurrent from noise light to improve the signal-to-noise ratio.

Dual inclined thin films on a substrate convert electromagnetic waves into thermal electromotive force.

A non-uniform insulating layer structure in an organic light-emitting display reduces electrical interference between wiring and the opposite electrode.

A photonic semiconductor package integrates waveguides and electronic dies via interposer structures for direct signal routing.

Rear-mounted driver integrated circuits eliminate front bezels, resolving visibility and resolution trade-offs in multi-display devices.

A light emitting diode uses a conductor passing through semiconductor layers to form channels and recesses via breakdown phenomena.

A galvanomagnetic sensor detects strut angular position using a magnet on an idler gear within the stator portion.

Selective wet etching of sacrificial pillars simplifies split memory cell formation, reducing manufacturing complexity and processing costs for 3D NAND devices.

A red host material with a specific photo-luminescence peak maximum aligns energy levels with the electron-transporting layer to optimize charge injection in organic light emitting displays.

External repair power supply fuses shorted lines between test points, eliminating the need for additional repair wiring and reducing manufacturing costs.

Variable thickness in the intermediate layer side areas prevents stripper penetration that damages the emission layer, reducing defective pixels.

Plasma deposition of metal monolayers enables atomic diffusion bonding between polished substrates in an ultra-high vacuum environment.

Multiple mirrors redirect reflected laser beams back onto target films, converting energy loss into additional crystallization heat.

Asymmetric spacer formation enables uniform recess depth control, reducing the short channel effect while maintaining device reliability.

Vertical capacitor plates spaced by the pixel definition layer increase capacitance without reducing the pixel aperture opening ratio.

Offsetting adjacent NAND strings decouples bitline pitch from cell pitch, doubling page size and restoring data throughput degraded by larger cell spacing.

Resin stress absorption units release bending forces to prevent thin film transistor fractures and improve substrate reliability.

Interface chip resolves signal management complexity in stacked memory devices by dividing channels and applying dynamic chip enable signals.

Recessed pixel electrode structures diffuse and bend emitted light paths to prevent color mixture between adjacent pixels in high-density displays.

A bank hole elongates the current leakage path between adjacent pixels, improving color reproduction rate.

Dynamic temperature control maintains adhesive integrity while accelerating curing speed, preventing flying dies in semiconductor packaging.

Sidewall deposition forms thermally confined phase change memory cells, resolving narrow trench filling difficulties.

A casing attachment structure uses sliding resistance between damping members to suppress vibration transmission.

An integrated photonic device segments phosphor conversion across multiple LEDs on a single substrate to generate full spectrum colors.

Stacked metal layers block ambient light to suppress noise currents while enhancing backscattering of radiation for higher detection sensitivity.

A permuting unit reorders active pen IC pads to process receive signals through time-segmented reception.

An exciplex light-emitting element transfers energy to a thermally activated delayed fluorescence material.

A latch circuit distributes latches by control signal order to configure pipe latches.

Ion beam etch redeposits a conductive liner on phase-change memory sidewalls to prevent GST oxidation and stabilize resistance.

Pre-formed repair lines merge with common electrodes to fix broken data lines without extra photolithography steps, maintaining image quality.

Spin-on carbon layer fills gaps between vertical channel transistor pillars to enable precise isolation trench etching.

A reflection layer with distinct high and low reflectance portions manages optical resonance within an electro-optical device.

A sacrificial layer protects front-side structures during semiconductor wafer backside stripping processes.

A compound-based organic electric element uses host-dopant energy transfer to boost luminous efficiency and color purity.

A semiconductor light emitting device uses a recessed light reflective sealing resin to cover element regions and fill substrate voids.

Re-press molding sintered powder mixtures to produce wavelength conversion members with precise dimensions and surface finish.

A semiconductor capping layer integrates with the channel layer to form a thicker contact area in 3D memory devices.

Selective epitaxial growth shrinks trench width to overcome deposition limits and increase capacitance density.