LDMOS Breakdown Protection Region for Peripheral Field Stress
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Solution Overview
Problem
LDMOS transistor devices face breakdown voltage degradation due to potential pinning at the edge or periphery, leading to reliability issues and early avalanche breakdown, especially in high-voltage applications, as charge inversion occurs along device isolation region walls, creating hot spots and increasing electric field stress.
Innovation Solution
A breakdown protection region, configured as a lightly doped ring, is disposed between the device isolation region and the body region, reducing pinning potential and electric field stress by interrupting charge carrier paths along the periphery, thereby preventing inversion and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a RESURF structure is used to increase breakdown voltage, then the electric field near the drift region is reduced, but breakdown still occurs at peripheral locations due to charge inversion at isolation region walls
Solution Approach 1:
A breakdown protection region is introduced as an intermediary structure between the device isolation region and the body region. This intermediate region, with its specific doping concentration and depth, acts as a mediator to reduce the electric field at the isolation wall interface and prevent charge inversion, thereby protecting against peripheral breakdown without interfering with the main drift region functionality
Solution Approach 2:
The breakdown protection region is implemented with spatially varying doping characteristics - it has a specific doping concentration range (1×10^16 to 1×10^18 atoms/cm³) and depth (0.5 to 2.0 micrometers) that differs from both the drift region and the isolation region. This local variation in doping quality creates an optimal electric field distribution that prevents peripheral breakdown while maintaining overall device performance
2Reliability
If the device isolation region is extended to improve breakdown protection, then peripheral breakdown is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The breakdown protection function is segmented into a separate, distinct region with specific doping characteristics rather than extending the isolation region. The breakdown protection region is defined by its own doping concentration range and depth parameters, creating a modular structure that simplifies the overall device architecture while maintaining effective peripheral protection
Solution Approach 2:
Instead of changing the geometric extent of the isolation region, the solution changes the doping parameters - specifically introducing a breakdown protection region with doping concentration between 1×10^16 to 1×10^18 atoms/cm³ at a depth of 0.5 to 2.0 micrometers. This parameter-based approach provides breakdown protection through material properties rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The breakdown protection region significantly increases the off-state breakdown voltage and voltage rating of LDMOS transistors by reducing pinning potential and electric field stress, delaying breakdown and minimizing leakage current, thus enhancing reliability in high-voltage operations.
Implementation Method 1
reducing pinning potential and electric field stress by interrupting charge carrier paths along the periphery
Implementation Method 2
charge inversion occurs along device isolation region walls, creating hot spots and increasing electric field stress
Implementation Method 3
delaying breakdown and minimizing leakage current, thus enhancing reliability in high-voltage operations
Data Source
AI summary
A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.