Vertical Channel Transistor Isolation Trench Formation
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Solution Overview
Problem
The integration of semiconductor devices is limited by the limitations in the fabrication process of vertical channel transistors, particularly due to mismatched photoresist patterns and isolation trench regions, leading to damage of nitride spacers and irregular trench widths, which hampers the increase in integration density.
Innovation Solution
A spin on carbon (SOC) layer is used to fill the gap between pillar patterns, and photoresist patterns wider than the trench width are formed to prevent mismatch, allowing for precise etching of the SOC layer and substrate to create consistent isolation trenches, minimizing spacer damage and ensuring proper etch barrier functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photoresist patterns are formed to define isolation trench regions, then the isolation trench can be etched to separate bit line impurity regions, but mismatch between photoresist patterns and trench regions occurs leading to damage of nitride spacers and irregular trench widths
Solution Approach 1:
A spin-on carbon (SOC) layer is deposited to fill the gap region between pillar patterns before forming photoresist patterns. This preliminary action creates a buffer layer that compensates for potential overlay misalignment, preventing direct exposure and damage to the nitride spacers during the etching process.
Solution Approach 2:
The SOC layer acts as an intermediary layer between the photoresist patterns and the nitride spacers. When etching occurs, this intermediate layer absorbs the misalignment stress and protects the critical nitride spacer structure from direct damage, ensuring both trench width consistency and spacer integrity.
2Reliability
If photoresist patterns are made wider to prevent mismatch, then spacer damage is reduced, but the 'not open' phenomenon occurs where the trench fails to fully form
Solution Approach 1:
The SOC layer is deposited in advance to fill the gap between pillars, creating a sacrificial buffer that allows wider photoresist patterns to be used without causing the 'not open' phenomenon. The etching process selectively removes the SOC layer where needed while protecting the nitride spacers.
Solution Approach 2:
The etching process parameters are optimized to selectively remove the SOC layer while preserving the nitride spacers. By controlling etch selectivity and depth, the method achieves complete trench formation (preventing 'not open') while maintaining spacer integrity through the protective SOC buffer.
3Productivity
If integration density is increased by reducing cell dimensions, then more devices fit on the wafer, but shorting effects such as DIBL, hot carrier effect, and punch through occur due to reduced channel length
Solution Approach 1:
The patent transitions from planar transistor geometry to vertical channel transistor structure. By changing the channel orientation from horizontal to vertical, the design achieves shorter cell footprint (improved integration density) while maintaining adequate channel length (preserved electrical stability) through the vertical dimension.
Solution Approach 2:
The substrate is divided into multiple isolated regions using the etched isolation trenches. This segmentation separates adjacent bit line impurity regions and vertical channel structures, preventing electrical interference and shorting effects while enabling high-density integration through compact cell layout.
Data Source
AI summary
A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.