Semiconductor Capping Layer for 3D Memory Contact Resistance
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Solution Overview
Problem
3D NVM devices face challenges in achieving effective control over memory cells due to the limited process window for forming metal contacts and increased contact resistance caused by voids in the silicide layer, which is exacerbated by the thinner channel layer.
Innovation Solution
A semiconductor capping layer is integrated with the channel layer to form a thicker contact area, allowing for a greater process window for metal contact formation and preventing voids in the silicide layer, while maintaining the channel thickness of memory cells on the sidewalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel layer thickness is reduced to control memory cells more effectively, then the control efficiency is improved, but the process window for forming metal contact is limited and voids occur in the silicide layer
Solution Approach 1:
The contact structure is segmented into multiple layers: channel layer, semiconductor capping layer, and metal contact layer. The semiconductor capping layer is introduced as a separate intermediate layer between the channel layer and metal contact, allowing the channel layer to remain thin for good control while providing an additional layer for contact formation process window.
Solution Approach 2:
The semiconductor capping layer acts as an intermediary layer between the channel layer and the metal contact. This intermediate layer prevents direct contact between metal and channel, avoiding silicide layer voids while maintaining electrical connection, thus solving the manufacturing precision issue without compromising control efficiency.
2Manufacturing precision
If a thicker contact area is formed to increase process window, then the process window is improved, but the channel thickness of memory cells increases
Solution Approach 1:
The vertical structure is segmented into distinct functional regions: the thin channel layer for memory cell control and the thicker semiconductor capping layer for contact formation. This segmentation allows each layer to have optimized thickness for its specific function without compromising the other.
Solution Approach 2:
The semiconductor capping layer provides locally increased thickness only at the contact area where metal contact is formed, while the channel layer maintains its thin thickness in the memory cell regions. This local quality enhancement solves the process window issue without increasing overall channel thickness.
Data Source
AI summary
A memory device comprises a patterned multi-layers stacking structure, a semiconductor capping layer, a memory layer and a channel layer. The patterned multi-layers stacking structure is formed on a substrate and has at least one trench used to define a plurality of ridge-shaped stacks comprising at least one conductive strip in the patterned multi-layers stacking structure. The semiconductor capping layer covers on the ridge-shaped stacks. The memory layer covers on sidewalls of the trench. The channel layer covers on the memory layer, the semiconductor capping layer and a bottom of the trench, wherein the channel layer is directly in contact with the semiconductor capping layer.