Back-Illuminated Image Sensor Wafer Bonding for Low-Aspect Connections
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices, such as solid-state imaging devices, face challenges in forming high-aspect ratio connection holes in substrates, which are costly and complicated, limiting the choice of connection conductor materials and increasing production costs, while also requiring specialized processing steps.
Innovation Solution
A method involving bonding half-finished semiconductor wafers with pixel arrays and logic circuits, thinning one wafer, and forming electric connections between them, allowing for the use of standard wafer manufacturing processes and reducing the aspect ratio of connection holes, thus enabling mass production and cost reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection holes are formed in completely finished functional chips, then electrical connection between chips is achieved, but the aspect ratio of connection holes becomes very high making the process costly and complicated
Solution Approach 1:
The patent applies preliminary action by bonding the first and second semiconductor wafers together in a half-finished state before completing all processing steps. Specifically, the first wafer is bonded to the second wafer before forming the connection holes, allowing the holes to be formed through a reduced thickness. This preliminary bonding action enables subsequent connection hole formation with much lower aspect ratios, avoiding the complexity of drilling through fully completed chips.
Solution Approach 2:
The patent segments the manufacturing process into distinct phases where different wafers are processed to different completion stages before bonding. The first semiconductor wafer is processed to a half-finished state with partial circuit structures, while the second wafer is processed separately. This segmentation allows each wafer to be optimized independently and enables connection holes to be formed through thinner combined structures rather than through fully completed thick chips.
2Reliability
If high-aspect ratio connection holes are formed in finished chips, then chip-to-chip electrical connection is achieved, but the choice of connection conductor materials is limited and production costs increase
Solution Approach 1:
By performing the wafer bonding action before completing all processing steps and before forming connection holes, the patent creates a structure where connection holes traverse a much shorter distance. This preliminary bonding enables the use of standard conductor materials and formation techniques that would be impossible if holes were drilled through fully completed thick chips, thereby expanding material choices and reducing costs.
3Productivity
If standard wafer manufacturing processes are used, then mass production and cost reduction are enabled, but connection holes must be formed after complete chip fabrication
Solution Approach 1:
The patent resequences the manufacturing operations by performing wafer bonding before completing all chip fabrication steps and before forming connection holes. This preliminary action allows connection holes to be formed through thinner structures with much lower aspect ratios, enabling the use of standard wafer processing techniques that support mass production rather than requiring specialized high-precision hole formation processes.
Solution Approach 2:
The patent introduces dynamic flexibility in the manufacturing sequence, allowing the process to adapt to standard wafer fabrication capabilities. By making the bonding operation occur at an intermediate stage rather than at a fixed point after completion, the process can dynamically adjust to use conventional manufacturing techniques, thereby improving productivity and enabling mass production while maintaining acceptable manufacturing precision.
4Reliability
If chips are completely built up before mounting, then functional performance is optimized, but specialized processing steps are required increasing production complexity
Solution Approach 1:
The patent applies preliminary action by bonding wafers at an intermediate stage before completing all processing steps on both wafers. This allows subsequent processing steps to be performed on the bonded structure using standard techniques, avoiding the need for specialized post-bonding processing that would be required if chips were fully completed before bonding. The preliminary bonding action simplifies subsequent manufacturing while preserving functional performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient formation of high-performance semiconductor devices with reduced production costs and simplified processing, enabling the use of various connection conductor materials and optimizing the performance of both imaging and logic circuits.
Implementation Method 1
bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together
Data Source
Figure 1
Figure 2A~2C
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AI summary
A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.