High-Voltage MOS Transistor Gate Structure for Cost Reduction
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Solution Overview
Problem
Conventional high-voltage-resistant MOS transistors with LDD structures face challenges in reducing manufacturing costs due to complex processes like photolithography and ion implantation, which increase processing time and cost, and struggle to form lightly doped diffusion regions with predetermined electrical strength.
Innovation Solution
A MOS transistor design featuring a gate electrode with separate opposition parts and a combination part, where lightly doped diffusion regions are formed using the gate electrode and element isolation oxide film as a mask, eliminating the need for a photolithographic process and reducing the number of ion implantation steps, allowing for self-aligned formation of heavily doped diffusion regions with uniform LDD length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process and ion implantation process are used to form lightly doped regions, then LDD length can be designed, but the number of processes increases and processing period increases, thus increasing manufacturing cost
Solution Approach 1:
The patent extracts and eliminates the photolithography process from the manufacturing flow by using a self-aligned ion implantation method. The gate electrode structure itself serves as the mask for defining the LDD region boundaries, removing the need for separate photolithography steps while maintaining precise LDD length control.
Solution Approach 2:
The gate electrode structure serves multiple functions: it acts as both the functional gate component and the mask for ion implantation. This multi-functionality eliminates the need for separate mask structures and photolithography processes, reducing the total number of manufacturing steps.
2Reliability
If ion implantation is performed at least twice to form lightly doped diffusion regions, then electrical strength can be controlled, but the processing period increases and manufacturing cost increases
Solution Approach 1:
The patent performs preliminary doping during the formation of the gate electrode structure. By incorporating dopant introduction at an early stage and using the gate structure as a self-aligned mask, the method achieves both lightly doped and heavily doped regions in a streamlined process, reducing the number of separate ion implantation steps required.
Solution Approach 2:
The patent combines multiple doping operations into a unified process flow. The self-aligned ion implantation method allows simultaneous or sequential formation of lightly doped and heavily doped regions without requiring separate photolithography and implantation cycles, effectively merging multiple steps into fewer operations.
3Ease of manufacture
If conventional MOS transistor structure is used, then manufacturing is simpler, but lightly doped diffusion regions cannot be formed with predetermined electrical strength
Solution Approach 1:
The gate electrode structure serves itself as the mask for ion implantation, eliminating the need for external photolithography processes. This self-aligned approach maintains manufacturing simplicity while achieving precise control over LDD region formation and electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and processing time by eliminating unnecessary steps, enabling the formation of high-voltage-resistant MOS transistors with consistent electrical strength and on-resistance, thereby improving cost effectiveness.
Implementation Method 1
a step of selectively implanting ionized atoms having a second conductive type opposed to the first conductive type onto a surface of the gate oxide film on which the gate electrode is not formed while utilizing the element isolation oxide film and the gate electrode as a mask
Implementation Method 2
a step of further implanting ionized atoms having the second conductive type into the pair of lightly doped diffusion regions and the element region positioned below the pair of lightly doped diffusion regions while utilizing the element isolation oxide film, and the residual sidewall insulating film as a mask
Data Source
AI summary
A high-voltage-resistant MOS transistor having high electrical strength and a method for manufacturing the same, whereby to effectively decrease cost of manufacturing, are provided. The gate electrode includes a pair of separate opposition parts and a combination part sandwiched by the pair of opposition parts so that the opposition parts are opposed to each other so as not to overlap with the element region and the combination part overlaps with the element region. Each length of the opposition parts in a junction direction is longer than that of the combination part. The sidewall insulating film is formed so as to be continuous between the opposition parts and partially overlap with the element region. Therefore, the number of processes and a processing period for forming the MOS transistor can be decreased and uniformity of LDD lengths of the MOS transistors can be improved.