3D NAND Memory Strings With Dummy TAVs for Reliable Coupling
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Solution Overview
Problem
Current memory circuitry designs face challenges in efficiently coupling channel material strings with conductor tiers in vertically-stacked memory cells, leading to potential defects and reduced performance, particularly in the stair-step structure of NAND architecture.
Innovation Solution
The implementation of a construction method involving vertically-alternating insulative and conductive tiers with channel openings that directly couple with the conductor tier, along with the use of dummy through-array-vias (TAVs) to enhance electrical connectivity and reduce electric field effects, thereby improving manufacturing and operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional coupling methods are used in stair-step structures, then manufacturing complexity is reduced, but electrical connectivity and reliability deteriorate
Solution Approach 1:
The patent introduces an intermediate conductive tier structure that acts as a mediator between the channel material strings and the main conductor tier. This intermediate structure provides a gradual transition zone that improves electrical coupling reliability while distributing the complexity across multiple manageable layers rather than requiring a single complex coupling mechanism.
Solution Approach 2:
The patent transitions from planar coupling methods to a three-dimensional vertically-stacked architecture with alternating insulative and conductive tiers. This dimensional change allows channel material strings to couple with conductor tiers through vertical stacking, improving electrical connectivity by creating multiple coupling paths and reducing reliance on single-point contacts in the stair-step structure.
2Reliability
If direct electrical coupling is implemented, then performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the coupling structure into multiple discrete alternating insulative and conductive tiers, with channel openings formed through specific sequences of these tiers. This segmentation allows each tier to be manufactured and aligned independently with tolerable precision, while the cumulative effect of multiple aligned segments achieves the required direct electrical coupling. The segmentation reduces the precision burden from a single complex alignment to multiple simpler, repeatable alignment steps.
3Productivity
If vertically-stacked memory cells are used, then integration density is improved, but defects in coupling structures increase
Solution Approach 1:
The patent applies local quality by creating alternating insulative and conductive tiers with distinct local properties. The insulative tiers provide electrical isolation where needed, while the conductive tiers provide coupling paths where needed. The channel openings are selectively formed through specific sequences of these tiers to create localized coupling regions. This local differentiation improves integration density by allowing dense vertical stacking while reducing defects by providing electrical isolation that prevents unwanted interactions and failure propagation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures direct and reliable electrical coupling of channel material strings with conductor tiers, reducing defects and enhancing the performance and reliability of memory circuitry, especially in complex stair-step structures.
Implementation Method 1
dummy through-array-vias (TAVs) to enhance electrical connectivity and reduce electric field effects
Implementation Method 2
Strings of memory cells comprise operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region. The operative channel-material strings directly electrically couple with conductor material of the conductor tier.
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from a memory-array region into a stair-step region. Strings of memory cells comprise operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region. The operative channel-material strings directly electrically couple with conductor material of the conductor tier. The individual laterally-spaced memory blocks comprise an intermediate region between the operative channel-material strings and the stair-step region. A dummy through-array-via (TAV) extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks. The dummy TAV is directly electrically coupled with the operative channel-material strings in its memory block. Other embodiments are disclosed.