Deep Level Impurity Region for Transistor Contact Resistivity
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Solution Overview
Problem
As semiconductor devices scale down, the contact resistance between silicide and silicon in source and drain regions increases, limiting device speed due to saturation levels of doping and the small silicide interface area, making it difficult to further improve device performance by scaling other parameters.
Innovation Solution
A deep level impurity region is formed at the upper portion of the doped semiconductor region in the source and drain areas, with a depth greater than or equal to the depletion width, to create a metal-semiconductor interface that reduces contact resistivity by providing an additional current path through deep level donors or acceptors, and a silicide metal contact is formed over this region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If devices are scaled down to reduce gate length and dielectric thickness, then device speed improves, but contact resistance increases due to smaller silicide interface area
Solution Approach 1:
The patent applies local quality by creating a deep level impurity region with specific doping characteristics at the upper portion of the doped semiconductor region. This localized modification of the semiconductor material properties (creating deep level donors or acceptors) provides an additional current path specifically at the metal-semiconductor interface, thereby reducing contact resistance in the critical contact area without affecting other device regions.
Solution Approach 2:
The patent changes the doping parameters by forming a deep level impurity region with doping concentration and depth specifically optimized to extend into the depletion width region. This parameter change creates band-bending effects and additional tunneling paths that reduce contact resistance, allowing the device to maintain low contact resistance even as the overall device dimensions are scaled down.
2Reliability
If doping level is increased to reduce contact resistance, then contact resistivity decreases, but doping is already at saturation levels in current CMOS technology
Solution Approach 1:
Instead of uniformly increasing doping throughout the source/drain region (which would be complex and already saturated), the patent applies local quality by creating a specific deep level impurity region at the upper portion. This localized approach provides the additional current path functionality exactly where needed at the metal-semiconductor interface, achieving contact resistance reduction without requiring complex global doping changes.
Solution Approach 2:
The deep level impurity region acts as an intermediary mechanism between the metal contact and the heavily doped semiconductor. It provides an additional tunneling path that mediates the charge transport, effectively reducing contact resistance through a intermediate physical mechanism rather than simply increasing the base doping level further.
3Length of moving object
If silicide interface area is reduced due to scaling, then device dimensions improve, but contact resistance increases in both relative and absolute terms
Solution Approach 1:
The patent changes the electrical parameters at the contact interface by introducing deep level impurities that create additional tunneling paths. This parameter change in the semiconductor material properties compensates for the reduced physical interface area, maintaining low contact resistance despite smaller device dimensions.
Solution Approach 2:
The contact structure effectively becomes composite in nature, combining the heavily doped semiconductor region with an additional deep level impurity region. This composite structure provides multiple current paths (through both the standard doped region and the deep level impurity region), compensating for the reduced contact area through enhanced material functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistivity by providing an extra tunneling path for electrons, thereby reducing the parasitic contact resistance and enabling faster device performance even as devices continue to scale down.
Implementation Method 1
effectively reduces contact resistivity by providing an extra tunneling path for electrons
Implementation Method 2
activating dopants in both the doped semiconductor region and the deep level impurity region by annealing
Implementation Method 3
During an annealing process, the atoms of silicon (Si) in the source and drain regions react with the atoms of the refractory metal, thereby forming a silicide layer
Data Source
AI summary
A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.