3D Semiconductor Device Stacked Substrates Crystal Orientation
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of processing equipment needed for fine pattern formation, making it challenging to increase their integration density, while three-dimensional semiconductor devices aim to overcome these limitations by stacking memory cells, but they require enhanced structural stability to maintain performance and cost-effectiveness.
Innovation Solution
A three-dimensional semiconductor device is designed with a stack structure featuring gate electrodes, channel regions penetrating the stack, and a peripheral circuit structure on interlayer dielectric layers, where the substrates have specific crystal plane orientations to enhance structural stability and electrical connectivity, allowing for increased integration density without the limitations of two-dimensional devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use finer patterns to increase integration, then integration density is improved, but processing equipment cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional stacked semiconductor devices. By stacking multiple active layers vertically, the integration density increases without requiring finer lateral patterns, thus avoiding the need for more expensive processing equipment while achieving higher device density.
2Quantity of substance
If three-dimensional semiconductor devices stack memory cells vertically, then integration density is improved, but structural stability deteriorates
Solution Approach 1:
The three-dimensional stacked structure is divided into multiple discrete active layers separated by interlayer dielectric layers. This segmentation allows each layer to be independently supported and reduces the cumulative stress and warpage that would occur in a monolithic stacked structure, thereby improving structural stability while maintaining high integration density.
Solution Approach 2:
Interlayer dielectric layers are introduced as intermediary materials between the stacked active layers. These dielectric layers act as stress buffers and mechanical separators, reducing the direct mechanical interaction between adjacent active layers and minimizing warpage, thus enhancing the overall structural stability of the three-dimensional device.
3Stability of the object's composition
If substrates have intersecting crystal directions, then structural stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the crystal orientation parameter of the substrates, specifically using substrates with intersecting crystal directions (e.g., <100> and <110> orientations). This parameter change reduces anisotropic stress and minimizes warpage in the stacked structure, improving structural stability. The manufacturing complexity increase is managed through standardized fabrication processes.
Data Source
AI summary
Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.