3D Memory Split Cells via Sacrificial Pillar Etching
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming split memory cells with complex structures, which complicates the manufacturing process and increases costs due to the need for multiple etching steps and precise layer formation.
Innovation Solution
A method of forming a three-dimensional memory device with alternating stacks of insulating and conductive layers, where memory openings are filled with a dielectric core and semiconductor channels, and sacrificial pillar structures are selectively etched to create split memory cells, simplifying the process through selective wet etching and reducing processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etching steps and precise layer formation are used to form split memory cells, then manufacturing precision is improved, but device complexity and processing costs increase
Solution Approach 1:
Sacrificial pillar structures are formed in advance before the memory opening fill structures are created. These sacrificial pillars serve as temporary placeholders that define the future locations of split memory cells. By performing this structural preparation beforehand, the subsequent formation of split memory cells becomes simpler and more precise, as the etching process only needs to remove the sacrificial material rather than create the entire structure from scratch.
Solution Approach 2:
Sacrificial pillar structures act as intermediary elements during the manufacturing process. These temporary structures facilitate the formation of split memory cells by providing a defined template that guides the subsequent etching steps. After the memory opening fill structures are formed around these sacrificial pillars, the sacrificial material is removed, leaving behind the desired split memory cell configuration. This intermediary approach simplifies the overall process by breaking down a complex formation task into manageable steps.
2Manufacturing precision
If multiple etching steps are used to form split memory cells, then manufacturing precision is improved, but processing time and costs increase
Solution Approach 1:
The formation of multiple split memory cells is achieved by merging the use of multiple sacrificial pillar structures within a single memory opening. Instead of performing separate etching operations for each split memory cell, the process combines all sacrificial pillar removal steps into one unified etching operation. This merging of operations maintains high manufacturing precision while significantly reducing the total processing time and associated costs.
3Quantity of substance
If complex structures with multiple layers are formed, then memory density is improved, but ease of manufacture deteriorates
Solution Approach 1:
The memory opening fill structure is segmented into multiple distinct components: a dielectric core, semiconductor channels, and memory films. These segmented elements are formed separately using the sacrificial pillar template, allowing each component to be optimized independently while maintaining overall manufacturing simplicity. The segmentation approach enables high memory density through multiple functional layers while keeping the manufacturing process manageable through systematic, step-by-step formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of split memory cells, decreases processing costs, and enables the creation of multilevel memory structures like monolithic three-dimensional NAND string memory devices with improved efficiency and reduced complexity.
Implementation Method 1
removing the sacrificial pillar structures selective to the in-process memory opening fill structures
Data Source
AI summary
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each of the alternating stacks laterally extend along a first horizontal direction, and neighboring pairs of the alternating stacks are laterally spaced apart along a horizontal direction by laterally alternating sequences of memory openings and dielectric pillar structures. Each of the memory openings contains a respective memory opening fill structure that includes a dielectric core, a first vertical semiconductor channel, a second vertical semiconductor channel, a first memory film, and a second memory film. The dielectric core contacts a pair of dielectric pillar structures among the dielectric pillar structures of the laterally alternating sequences.