Modular IC Tile Design for Parasitic Reduction
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Solution Overview
Problem
Traditional integrated circuit (IC) design and layout face challenges such as parasitic resistance, capacitance, and inductance issues due to internal routing and wire bond connections, leading to space inefficiency and high development costs, as well as limitations in reconfigurability and flexibility for creating new products.
Innovation Solution
A modular design approach using standardized, programmable tiles with embedded I/O terminals and interface circuitry, allowing for flexible reconfiguration and direct connection to printed circuit boards without intermediate carriers, reducing parasitics and enabling rapid development of application-specific ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wire bond packaging is used, then I/O terminals can be connected to package pins, but parasitic resistance, capacitance and inductance increase and space is wasted
Solution Approach 1:
The patent extracts and eliminates the wire bond and package lead intermediaries from the signal path. By using flip-chip CSP technology, the I/O terminals are directly connected to solder bumps that attach to the PCB, removing the harmful wire bonds and package leads that generate parasitics. This extraction of unnecessary components directly reduces parasitic resistance, capacitance and inductance while improving signal quality.
2Adaptability or versatility
If functional blocks are added to modify existing products, then product functionality is improved, but re-layout time and development cost increase
Solution Approach 1:
The patent segments the IC into distinct functional blocks, each with its own I/O terminals and capabilities. This segmentation allows individual functional blocks to be independently selected, added, or removed without requiring complete re-layout of the entire IC. The modular architecture enables rapid product configuration by simply changing which functional blocks are included in the final design.
Solution Approach 2:
The patent creates a universal IC platform with multiple functional blocks that can serve different purposes. The same basic IC structure can be configured for various applications by selectively enabling different functional blocks through software or configuration bits, eliminating the need for physical re-layout and enabling rapid adaptation to different market requirements.
3Adaptability or versatility
If functional blocks are removed by disabling circuitry, then product configuration is simplified, but die size and cost are not optimal
Solution Approach 1:
The patent applies local quality by allowing different regions of the IC (individual functional blocks) to have different states of activation. Rather than disabling circuitry throughout the entire die, only the specific functional blocks that are not needed for the current application remain inactive, while other blocks continue to operate at full capacity. This enables optimal utilization of the die area for each specific application.
4Reliability
If internal routing is used to connect functional blocks to I/O pads, then circuit functionality is achieved, but parasitic resistance, capacitance and inductance increase
Solution Approach 1:
The patent transitions from two-dimensional planar routing to three-dimensional vertical connections through the use of through-silicon vias and embedded I/O terminals. By moving I/O terminals into the bulk of the silicon substrate and using vertical via structures, the patent creates shorter, more direct signal paths that reduce parasitic effects compared to traditional surface-level routing.
Data Source
AI summary
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.