Semiconductor Gate Electrode Support Patterns for Pitch Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device fabrication, particularly with fine pitch and highly integrated designs, there is a challenge in controlling the pitch between patterns, leading to difficulties in accurate overlay during the fin cut process due to small process margins and the complexity of forming fine patterns using double and quad-patterning technologies.
Innovation Solution
A method involving the sequential formation of gate and mandrel layers, followed by the creation of spacer patterns and sacrificial layers, and the use of photoresists to form gate patterns, which includes a support structure to prevent leaning of gate electrodes and improve pitch control, allowing for the formation of semiconductor devices with various pitches without requiring adjustments in the gap between patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If double-patterning technology (DPT) and quad-patterning technology (QPT) are used to form fine patterns, then the pitch and width of patterns can be reduced, but the process complexity and difficulty of controlling pitch increase
Solution Approach 1:
The patent segments the patterning process into multiple distinct stages: forming mandrels with first photoresist, creating spacers with second photoresist, and forming final patterns with third photoresist. Each stage uses a different photoresist layer with specific properties optimized for that stage, thereby reducing the complexity of each individual step while achieving the overall fine pitch pattern formation.
Solution Approach 2:
The patent introduces a vertical dimension by forming three-dimensional structures including mandrels, spacers, and support patterns at different heights and positions. The support pattern extends in the vertical direction to provide mechanical support, creating a multi-layered structure that solves the pitch control problem through spatial arrangement rather than relying solely on planar process complexity.
2Adaptability or versatility
If fine pitch patterns are formed using DPT and QPT, then various fine patterns can be created, but the overlay accuracy during fin cut process deteriorates due to small process margins
Solution Approach 1:
The patent introduces support patterns as intermediary structures that physically connect and stabilize adjacent gate patterns. These support patterns act as mediators that prevent leaning and improve overlay accuracy during the fin cut process, allowing various fine patterns to be formed while maintaining manufacturing precision through enhanced structural stability.
Solution Approach 2:
The support patterns are formed in advance before the fin cut process to provide preemptive structural reinforcement. By creating these support structures beforehand, the patent cushions against potential overlay errors and leaning issues that would otherwise occur during subsequent processing steps, thereby maintaining precision even with varied fine patterns.
3Productivity
If gate patterns are formed with fine pitch, then high integration is achieved, but gate electrode leaning occurs reducing reliability
Solution Approach 1:
The patent applies local quality by providing support patterns selectively at specific locations where gate electrodes are most susceptible to leaning. The support patterns are positioned adjacent to gate patterns and extend in the vertical direction to provide localized reinforcement exactly where needed, rather than uniformly throughout the entire structure, thereby maintaining high integration while improving reliability at critical points.
Solution Approach 2:
The patent creates a composite structure combining gate patterns with support patterns formed from different materials with complementary properties. The support patterns use materials selected for their mechanical strength and stability to counteract leaning, while the gate patterns use materials optimized for electrical performance, creating a composite system that achieves both high integration and enhanced reliability.
Data Source
AI summary
A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.