Box-Shaped Gate Structure for DRAM Integration Density
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Solution Overview
Problem
The increasing chip size of semiconductor memory devices, particularly DRAM, leads to reduced productivity due to the passing gate effect, where gates crossing active regions can interfere with voltage conditions and cause '0' failures in word line disturb tests, especially in the 6F2 layout structure.
Innovation Solution
A semiconductor device with a modified gate structure where gates are formed in a box shape to obliquely cross two active regions, with no gate disposed between adjacent active regions, and buried gates are used to prevent the passing gate effect by ensuring that each gate only extends over the active regions where cell channels are formed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gates are formed in a line shape to orthogonally cross active regions in a 6F2 layout structure, then integration density is increased, but passing gate effect is generated causing voltage interference and reliability degradation
Solution Approach 1:
The gate structure is segmented into multiple discrete gate portions rather than a continuous line-shaped gate. Each gate portion is positioned over specific active regions, creating separate gate segments that prevent the passing gate effect while maintaining high integration density through the 6F2 layout arrangement.
Solution Approach 2:
The gate structure is extracted from the device isolation region and repositioned to extend only over the active regions. This removes the harmful passing gate effect that occurs when gates pass through device isolation regions, while preserving the orthogonal crossing configuration needed for high-density integration.
2Quantity of substance
If chip size is increased to accommodate more memory cells, then productivity is reduced, but cell area reduction through layout change to 6F2 structure improves integration
Solution Approach 1:
The gate structure implements local quality by having different configurations in different regions: gates extend over active regions to provide proper channel control, but do not extend into device isolation regions to avoid passing gate effects. This localized differentiation enables high-density 6F2 layout while maintaining device reliability.
3Adaptability or versatility
If gates extend over device isolation regions to pass through active regions, then layout flexibility is improved, but voltage interference between adjacent active regions occurs
Solution Approach 1:
The gate structure acts as an intermediary element that is strategically positioned only over active regions where channel formation is needed. By using the active region boundaries as natural delimiters, the gate provides necessary electrical control without creating harmful voltage interference in device isolation regions, thus mediating between layout flexibility and electrical isolation requirements.
Data Source
AI summary
A semiconductor device includes active regions defined by a device isolation layer, gates disposed in the active regions of cell channel regions, word lines disposed on the gates and extending along a first direction, and gate contacts configured to connect the gates to the word lines. The gates have a box shape which extends over two active regions.