Discrete 3D Processor With Split Memory-Logic Die Architecture
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Solution Overview
Problem
Conventional processors, based on two-dimensional integration and von Neumann architecture, face inefficiencies in mathematical computing, computer simulation, pattern processing, and neural networks due to limited internal memory, narrow system bus bandwidth, and inability to implement non-arithmetic functions effectively.
Innovation Solution
A discrete 3-D processor design that de-integrates 2-D and 3-D circuits, partitioning them into separate dice for optimized performance, featuring a plurality of storage-processing units with 3D-M arrays and logic circuits, allowing for increased computational density and flexibility by separating memory and logic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2-D integration is used with von Neumann architecture, then manufacturing simplicity is maintained, but computational density and processing performance are limited
Solution Approach 1:
The patent transitions from conventional 2-D planar integration to 3-D vertical stacking architecture. Multiple logic circuit layers and memory layers are stacked vertically to increase computational density and processing performance without proportionally increasing footprint area, thereby resolving the contradiction between productivity improvement and device complexity
Solution Approach 2:
The processor is segmented into multiple functional layers including logic circuit layers, memory layers, and interconnect layers. Each layer performs specific functions and is optimized independently, allowing complex 3-D integration to be managed through modular segmentation while maintaining high computational density
2Quantity of substance
If logic circuit and memory are disposed on the same plane, then device simplicity is maintained, but internal memory capacity is limited
Solution Approach 1:
Memory layers are stacked vertically above logic circuit layers in the 3-D architecture, increasing internal memory capacity by utilizing the vertical dimension rather than expanding horizontally. This multiplies the effective memory capacity without proportionally increasing the device footprint
Solution Approach 2:
The patent merges logic circuits and memory into a unified 3-D integrated structure where both functions coexist in close proximity through vertical stacking. This integration maintains functional unity while dramatically increasing memory capacity through the third dimension
3Speed
If processor and external memory are physically separated, then functional modularity is maintained, but data transfer bandwidth is limited
Solution Approach 1:
The patent combines previously separate processor and memory functions into a single integrated 3-D processor die. Memory layers are embedded within the processor structure, eliminating the need for external memory connections and dramatically increasing data transfer bandwidth by removing the external interface bottleneck
Solution Approach 2:
Multiple intermediate interconnect layers are introduced between logic and memory layers to facilitate high-speed data transfer. These intermediary structures provide parallel data pathways that increase effective bandwidth while managing the complexity of 3-D signal routing
4Adaptability or versatility
If 2-D integration is used, then manufacturing simplicity is maintained, but computational performance for non-arithmetic functions is insufficient
Solution Approach 1:
The processor is segmented into specialized functional units including arithmetic logic units, neural network processing units, and configurable logic blocks. Each unit is optimized for specific function types, enabling versatile non-arithmetic computations while managing complexity through functional decomposition
Solution Approach 2:
The 3-D architecture incorporates universal processing elements that can be configured for different computational tasks through programmable interconnects and configurable logic. This multi-functionality enables the processor to handle diverse non-arithmetic functions including neural networks, signal processing, and cryptographic operations
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.