Cascode Source Follower Circuit for Higher PSRR and SNR

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Solution Overview

Problem

Conventional source follower circuits have limited power supply noise suppression capabilities, which restricts their ability to enhance the signal-to-noise ratio (SNR) due to ineffective rejection of power supply noise.

Innovation Solution

The proposed source follower circuit employs a cascode configuration with transistors and capacitors to form voltage divider circuits, isolating power supply noise from the gate of the main source follower transistor, thereby increasing the power supply rejection ratio (PSRR) and SNR by ensuring that noise is not reflected in the output signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional source follower circuit is used, then the circuit structure is simple, but the power supply rejection ratio (PSRR) is limited

Engineering Contradiction:
Improvepower supply rejection ratioVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source follower circuit is segmented into two transistors (M1 and M2) arranged in a cascode configuration. Transistor M1 serves as a buffer between the power supply and M2, separating the noise rejection function from the signal following function. This segmentation allows M1 to suppress power supply noise while M2 maintains the source follower operation, thereby improving PSRR without significantly complicating the overall circuit structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Transistor M1 acts as an intermediary element between the power supply and the main source follower transistor M2. It mediates the transmission of power supply noise by providing a low-impedance path to ground for noise signals, preventing them from reaching M2 and degrading the output signal quality. This intermediary approach effectively improves PSRR while maintaining circuit simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If power supply noise suppression is enhanced in a source follower, then the signal-to-noise ratio (SNR) improves, but the circuit complexity increases

Engineering Contradiction:
Improvesignal-to-noise ratioVSAvoidcircuit configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The circuit segments the noise suppression function into a dedicated buffer transistor M1, which handles power supply noise independently. This allows M2 to focus on signal following with high SNR performance. The segmentation achieves improved SNR without requiring complex filtering or shielding circuits, as the noise rejection is inherently provided by the cascode structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cascode configuration enables the circuit to self-service noise suppression through the natural impedance characteristics of the transistors. M1's low output impedance automatically suppresses power supply noise without requiring external noise filtering components. This self-service approach improves SNR while avoiding additional circuit complexity from external noise suppression components.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20230307476A1Source follower circuit
Publication Date: 2023.09.28 REALTEK SEMICON CORP
  • US20230307476A1 patent drawing
  • US20230307476A1 patent drawing
  • US20230307476A1 patent drawing

AI summary

The present application discloses a source follower circuit, arranged for generating output signal according to input signal. The circuit includes: a first transistor having a drain coupled to a first reference voltage; a second transistor having a drain coupled to a source of the first transistor, and the first transistor and the second transistor both have polarization of a first type; a first capacitor, coupled between a gate of the first transistor and the input signal; and a first resistor, coupled between the gate of the first transistor and a first bias voltage; wherein a gate of the second transistor is coupled to the input signal, and a source of the second transistor outputs the output signal.