Vertical Memory Device Gate Length Control via Conformal Word Lines
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Solution Overview
Problem
Vertical semiconductor memory devices face challenges in controlling gate length, forming high-density bit lines, and integrating word lines due to difficulties in scaling down and manufacturing processes, particularly with single-crystalline channel materials.
Innovation Solution
A semiconductor memory device with pillar-shaped active regions and self-aligned gate stacks, where bit lines are buried below the active regions and word lines are formed in a conformal manner along the periphery of memory cells, allowing for precise control of gate length and high-density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical device structure is adopted to enable scaling down, then device density is improved, but gate length control becomes difficult
Solution Approach 1:
The patent transitions from planar gate structure to three-dimensional gate-all-around structure, where the gate wraps around the channel from all directions. This dimensional change enables precise gate length control through vertical epitaxial growth processes while achieving higher device density through vertical stacking of multiple channels.
Solution Approach 2:
The patent employs preliminary patterning of sacrificial layers and template structures before forming the final gate structure. This preliminary action establishes precise spatial definitions that guide subsequent epitaxial growth, ensuring accurate gate length control is achieved before the actual channel formation occurs.
2Reliability
If single-crystalline channel material is used to enhance performance, then carrier mobility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent replaces mechanical patterning and lithography processes with epitaxial growth methods to form single-crystalline channels. This substitution eliminates the need for complex lithographic steps while maintaining single-crystal quality, thereby reducing manufacturing complexity while preserving high carrier mobility.
Solution Approach 2:
The patent utilizes changes in epitaxial growth parameters such as temperature, pressure, and gas flow rates to control crystal orientation and material composition. By precisely adjusting these parameters, single-crystalline structures with desired properties are formed through a relatively simple continuous growth process rather than complex multi-step fabrication.
3Quantity of substance
If buried bit lines are formed below vertical transistors to increase density, then bit line density is improved, but integration difficulty increases
Solution Approach 1:
The patent implements a nested structure where bit lines are embedded within the vertical stack architecture. The bit lines are positioned at multiple levels within the three-dimensional structure, nesting multiple conductive paths within the vertical transistor columns, thereby achieving high density without requiring complex lateral routing.
Solution Approach 2:
The patent moves bit line routing from a two-dimensional planar layout to a three-dimensional vertical arrangement. Bit lines are formed at different heights and positions within the vertical stack, utilizing the vertical dimension to increase routing capacity and density while simplifying the lateral integration process.
4Area of stationary object
If word lines are extended conformally along periphery of memory cells to reduce footprint, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication processes where the conformal word line structures are automatically positioned relative to the memory cell periphery through in-situ growth or deposition. The structure serves its own alignment function, eliminating the need for separate high-precision alignment steps and reducing manufacturing precision requirements while achieving compact footprint.
Data Source
AI summary
A semiconductor memory device including a substrate; an array of memory cells arranged in rows and columns on the substrate, each memory cell comprising a vertical pillar-shaped active region having upper and lower source/drain regions and a channel region, and a gate stack formed around the channel region; a plurality of bit lines on the substrate, each bit line located below a column of memory cells and electrically connected to the lower source/drain regions of the memory cells; and a plurality of word lines on the substrate, each word line extending in a row direction and connected to gate conductors of the memory cells in a row of memory cells, each word line comprising first portions extending along peripheries of the memory cells and second portions extending between the first portions, the first portions of the word line extending in a conformal manner with sidewalls of the upper source/drain regions.