Memory Resistive Layer Layout for Cell and Via Resistance Control
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Solution Overview
Problem
Existing memory devices face challenges in optimizing resistive materials for both memory cells and access lines, as excessive resistive material can reduce efficiency, and achieving an optimal amount for each component is difficult with current deposition methods.
Innovation Solution
The use of separate resistive layers for memory cells and conductive vias allows for independent optimization of resistive material amounts, with a first resistive material layer deposited before the array termination etch and a second layer deposited after the conductive via formation, ensuring optimal resistance for both memory cells and access lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistive material is deposited to protect against high current stresses, then reliability is improved, but device efficiency deteriorates due to excessive resistance
Solution Approach 1:
The patent divides the resistive material deposition into separate layers: a first resistive material layer deposited before array termination etch for memory cell protection, and a second resistive material layer deposited after conductive via formation for access line protection. This segmentation allows independent optimization of resistive material amounts for different components, preventing excessive resistance in access lines while maintaining adequate protection for memory cells.
Solution Approach 2:
The patent applies different amounts of resistive material to different locations: the first resistive material layer is removed over conductive vias to minimize resistance in access lines, while the second resistive material layer is deposited only over conductive vias to provide localized protection. This local quality approach ensures optimal resistance characteristics in each region rather than uniform application.
2Manufacturing precision
If separate resistive layers are used for memory cells and access lines, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the resistive material deposition process into two distinct layers with different deposition timings and locations. The first layer is deposited before array termination etch and selectively removed over vias, while the second layer is deposited after via formation and applied only over vias. This segmentation enables precise control of resistive material distribution, achieving optimal resistance values for both memory cells and access lines despite the increased number of layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of optimized resistive material amounts for memory cells and access lines, improving device efficiency and reducing the risk of tile or block damage during manufacturing, while maintaining high memory cell density and performance.
Implementation Method 1
depositing a first resistive material on a set of memory stacks
Implementation Method 2
an area of the set of memory stacks is removed to form a gap in the first resistive material, the first conductive material, and one or more memory stacks of the set of memory stacks
Implementation Method 3
depositing, over the first conductive material and the conductive via, a second resistive material
Data Source
AI summary
A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.