Stress Buffer Layer Prevents Substrate Warpage in 3D Memory
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Solution Overview
Problem
In the fabrication of three-dimensional semiconductor memory devices, the substrate often experiences warpage due to stress from the deposition and patterning of various layers, leading to process failures and poor electrical characteristics.
Innovation Solution
A stress buffer layer is introduced, formed on top of the substrate, which enhances its rigidity and prevents warping by being patterned together with the gate stack to have a staircase shape, thereby maintaining the substrate's flatness during the formation of vertical channels and other features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple insulating and conductive layers are deposited and patterned on the substrate to form three-dimensional features, then the device functionality is improved, but substrate warpage occurs leading to process failures
Solution Approach 1:
The stress buffer layer is formed on the substrate before the deposition and patterning of multiple insulating and conductive layers. This preliminary action prevents substrate warpage from developing during subsequent fabrication processes, thereby maintaining process success rate while enabling three-dimensional device functionality.
Solution Approach 2:
The stress buffer layer acts as an intermediary between the substrate and the stacked insulating and conductive layers. It mediates the stress interactions by absorbing or distributing mechanical stresses, preventing warpage propagation to the substrate while allowing the formation of complex multi-layer structures.
2Reliability
If the substrate remains flat throughout fabrication, then process reliability is improved, but the complexity of maintaining flatness increases
Solution Approach 1:
The stress buffer layer automatically compensates for stresses generated during layer deposition and patterning without requiring external intervention. It self-adjusts to maintain substrate flatness throughout the fabrication process, improving process reliability without adding significant fabrication complexity.
3Shape
If a stress buffer layer is added to prevent warpage, then substrate flatness is improved, but the device structure becomes more complex
Solution Approach 1:
The stress buffer layer is selectively formed only in regions where stress compensation is needed, rather than uniformly across the entire device structure. This localized approach maintains substrate flatness where required while minimizing the overall structural complexity and material usage.
Data Source
AI summary
A semiconductor memory device includes a substrate having a cell region and a peripheral region, a gate stack including a plurality of insulating layers and a plurality of gates alternately stacked on the cell region of the substrate, a stress buffer layer on the gate stack, a vertical channel that extends vertically through the gate stack and is electrically connected to the substrate, a memory layer wrapped around the vertical channel. A bit line electrically connected to the vertical channel may be provided on the gate stack. In a method of fabricating a semiconductor device, the buffer stress layer is formed directly on an upper insulating layer of a stack whose shape is altered to form the gate stack to inhibit warping of the substrate during fabrication of the device.