3D CMOS Stacked Substrates for Transistor Density
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Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication, 2D transistor scaling faces challenges due to manufacturing variability and electrostatic limitations, limiting further density increases, prompting the need for 3D integration to stack transistors and enhance transistor density in volume rather than area.
Innovation Solution
A high-performance 3D CMOS device architecture is developed, allowing for the combination and stacking of multiple substrates with optimized processing parameters for low-voltage (LV) and high-voltage (HV) CMOS devices, along with 3D NAND memory, enabling the integration of 2D and 3D devices on the same transistor plane and allowing for separate processing of LV and HV devices to achieve maximum performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D transistor scaling is continued to increase transistor density, then transistor density per unit area improves, but manufacturing variability and electrostatic limitations worsen
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-stacked transistors, moving the scaling approach from lateral (area-based) to vertical (volume-based). This dimensional change allows continued density improvement without suffering from the same manufacturing variability and electrostatic limitations that plague scaled 2D transistors, as the vertical architecture maintains better control over channel dimensions and reduces sensitivity to lateral patterning variations.
2Ease of manufacture
If single wafer fabrication is used for all device types, then manufacturing process simplicity improves, but device performance optimization worsens
Solution Approach 1:
The patent divides the fabrication process into separate wafer stages: first wafers are dedicated to HV device fabrication with optimized high-voltage processing conditions, while second wafers are dedicated to LV device and memory fabrication with optimized low-voltage processing conditions. This segmentation allows each device type to receive tailored process optimization, improving overall device performance and reliability while maintaining manufacturing efficiency through specialized processing lines.
Data Source
AI summary
Techniques herein include methods of forming circuits by combining multiple substrates. High voltage devices are fabricated on a first wafer, and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.