Solid-State Devices TRIZ Cases

An interval layer segments the light-emitting layer to reduce peeling time and prevent color crossing between subpixels.

A light shielding film covers the front surface of a back-incident semiconductor substrate to block external light.

Silicon nanorod arrays detect incident light through optical resonance, resolving thermal reliability issues in sub-micron pixel sensors.

Reduced gate extension thickness minimizes interference between data storage areas while maintaining high integration density.

Shielding electrodes placed above gate and data lines intercept transient electromagnetic interference, protecting pixel electrodes from voltage fluctuations.

A tandem organic light emitting diode incorporates a mixed conductive charge generation layer combining high and low conductivity materials.

Equidistant active areas maintain constant matrix pitch, reducing projection optical aberrations during lithographic definition.

A pixel definition layer disperses hydrophobic particles to prevent ink cross-contamination while facilitating proper spreading.

A dual gate memory cell design with a channel body depth under 30 nanometers and an effective channel length greater than two-thirds the depth.

A lateral double diffused metal oxide semiconductor device integrates a junction field effect transistor to adjust gate voltage.

An AlGaN layer with controlled composition suppresses the quantum-confined Stark effect to resolve low luminance in long-wavelength emission.

Buried poly-silicon contacts prevent substrate damage and noise while enhancing short-wavelength sensitivity.

Merging three color emission layers into one reduces manufacturing complexity and driving voltage while maintaining full-color display capability.

Nested optical detection units within black matrix projections preserve aperture ratio while enabling accurate luminance compensation.

Segmented processing prevents etching residues on peripheral isolation structures while enlarging floating gate surface area to improve coupling ratio.

Asymmetric red, green, and blue emission regions increase aperture ratio in high-resolution organic light emitting displays.

Thick photoresist prevents depletion during repeated etching cycles, enabling high-layer 3D memory stack formation without frequent reapplication.

A driving semiconductor layer with a non-linear shape forms gate electrodes and storage capacitors on separate layers to expand voltage control.

Formula I host compounds with photoactive dopants boost efficiency while extending device longevity.

A pixel defining layer incorporates a hindered amine light stabilizer to scavenge radicals within an organic electroluminescence display.

A composite top electrode with a titanium nitride film eliminates interfacial oxide formation, reducing RC delay in memory cells.

Reflowable metal layers join microelectronic elements to resolve planarity challenges, reducing signal propagation delays in dense chip arrangements.

A reusable template aligns integrated circuit units on a holding ring during sputtering.

Peripheral crack-stopper structures guide dielectric cracking away from active OLED pixels during panel dicing.

A variable resistive memory device uses a matrix arrangement of cells with individual selection devices to enable independent data access.

Bonding arm CCD imagers align flip chip connector terminals with substrate pads, eliminating iterative fiducial mark detection to reduce alignment time.

A low resistance line connected to the cathode electrode through a contact hole minimizes lateral leakage in electroluminescence displays.

Integrating a color filter between electrode layers simplifies the substrate structure and reduces manufacturing complexity while improving touch sensitivity.

A single-sided conductive liner stabilizes resistance drift in phase change memory cells while minimizing RIE damage during fabrication.

A demodulator uses a noise-shaping modulator to generate quantized phase calibration values for MEMS gyroscopes.

A reflective polarizer and absorbing polarizer stack manages light polarization in display assemblies.

A depletion layer in an amplifying MOS transistor isolates the channel from substrate bias effects to enhance signal gain.

A connection wire electrically links defective OLED pixels to adjacent normal pixels for signal transmission.

A kink current calculation method for SOI devices extracts impact ionization and parasitic transistor factors to model channel length effects.

Vacuum encapsulation removes air from molding chambers to prevent bubbles and ensure complete insulation.

Embedded light-blocking regions in the transparent cover reduce optical cross-talk and stray light interference, improving signal-to-noise ratio.

ROM memory cells use diffusion and contact layers to program data, reducing bitline capacitance for faster access times.

Microwave irradiation crystallizes amorphous semiconductor films into polycrystalline structures with larger grain diameters.

Prevent anisotropic conductive film overflow from reducing module yield by containing adhesive in non-display area grooves.

Selective emitter implant increases germanium concentration at the bipolar transistor junction, achieving high gain without excessive process complexity.

A composite host system balances electron and hole transport to resolve emission region bias and extend device lifetime.

Asymmetric stacked microelectronic packages utilize wire bonding to reduce footprint and height while resolving co-planarity issues.

Plasma chemical vapor deposition forms a superhydrophobic thin film on organic light emitting diode displays.

Prismatic cristobalite filler in epoxy resin reduces warpage in asymmetric packages while maintaining flame retardancy without halogen additives.

A 3D CMOS architecture stacks multiple substrates to integrate high voltage and low voltage devices on separate wafers.

A thin film transistor substrate design with a passivation layer contact hole configuration that exposes drain electrode extended portions.

Forming vertical semiconductor channels through multi-tier memory films using sacrificial dielectric liners and selective etching.

Printed metal precursor ink forms silicide contacts and interconnects in a single step without etching.