Single-Sided Liner PCM Cell for 3D Crossbar Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating crosspoint memory arrays is to minimize the number of masking and processing steps while ensuring the reliability of phase change memory (PCM) cells, particularly addressing resistance drift issues and avoiding damage to the phase change material during Reactive Ion Etching (RIE).
Innovation Solution
A crosspoint memory structure with a single-sided conductive liner is implemented, using a fill-in process flow within the sacrificial masking layer of the etched access device to minimize exposure to RIE chemistry, and incorporating a Rs tuned liner on one side of the PCM cell to stabilize resistance and prevent drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single patterning using Reactive Ion Etching (RIE) is used to minimize masking layers and processing steps, then the number of masking steps and processing steps is reduced, but the phase change material may be damaged or modified during the RIE process
Solution Approach 1:
A liner layer is introduced as an intermediary between the RIE process and the phase change material. The liner is selectively removed after etching, allowing the RIE to proceed without directly exposing or damaging the phase change material, thus protecting it while enabling single patterning
Solution Approach 2:
The etching process is segmented into two distinct steps: first etching through the liner layer to define the access device, then selectively removing the liner to expose the phase change material without further RIE exposure. This segmentation protects the sensitive material while achieving the desired patterning
2Reliability
If an Rs tuned liner is included in the PCM cell to mitigate resistance drift, then resistance drift is stabilized, but the lowest achievable resistance is increased and the liner resistance becomes difficult to control
Solution Approach 1:
The liner is applied selectively only to specific regions where resistance drift mitigation is needed, rather than uniformly across the entire device. This localized application allows resistance tuning in critical areas while maintaining low resistance in other regions, achieving both drift stability and overall low resistance
Solution Approach 2:
The resistance of the liner is controlled by adjusting its thickness parameter. By precisely controlling the liner thickness during deposition, the resistance can be tuned to achieve the desired drift compensation while maintaining overall device performance, transforming the difficult-to-control non-linear relationship into a manageable parameter
Data Source
AI summary
A cross-point memory array and stacked memory array structure. The memory array includes a plurality of first conductive line structures formed in a dielectric material layer; a plurality of memory elements, each memory element including a fill-in phase change memory (PCM) cell, and an access device enabling read or write access to said memory PCM structure; a plurality of second conductive line structures, the plurality of second conductive structures perpendicularly oriented relative to the plurality of first conductive structures. An individual memory element of the plurality of memory elements is conductively connected at a respective intersection between a first conductive line structure and a second conductive line structure. Each phase change memory (PCM) cell of a memory element at an intersection having a sub-lithographic conductive tuning liner disposed on only one sidewall of the PCM cell. The manufacturing maintains a minimal number of masking and processing steps.