Stacked Microelectronic Packages Asymmetric Substrates
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Solution Overview
Problem
Existing stacked microelectronic device packages face challenges such as excessive space requirements for interconnections, preclusion of separate quality control testing, and co-planarity issues, which hinder the reduction of device footprint and increase in component density.
Innovation Solution
A microelectronic package design featuring two dies in a single package with one substrate being larger than the other, allowing for separate testing and back-to-back placement to avoid co-planarity issues, and utilizing wire bonding for electrical connections between substrates, enabling efficient stacking and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple microelectronic devices are stacked to increase component density, then the footprint is reduced, but excessive space is required for interconnections on the substrates
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by stacking packages. The interconnections extend through the substrate thickness rather than spreading across the surface, converting a two-dimensional area problem into a three-dimensional volume solution. This allows high-density interconnection without increasing footprint.
2Area of moving object
If stacked packages are used to reduce footprint, then space is saved, but separate quality control testing of devices is precluded
Solution Approach 1:
The patent divides the manufacturing and testing process into discrete stages: individual package assembly and testing, then subsequent stacking. This segmentation allows each package to be fully tested and qualified independently before being combined into the stacked configuration, maintaining quality control capability while achieving footprint reduction through stacking.
3Quantity of substance
If stacked packages are used to increase component density, then space utilization improves, but co-planarity issues arise
Solution Approach 1:
The patent employs asymmetric substrate thicknesses in the stacked packages, where adjacent packages have different substrate thicknesses. This asymmetry intentionally breaks co-planarity between stacked packages, allowing each package to be optimized independently for its specific electrical and mechanical requirements without being constrained by the need for perfect co-planarity across the stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for separate quality control testing of dies before assembly, reduces package height, and maintains compatibility with existing equipment, enhancing manufacturing yield and component density within a limited space.
Implementation Method 1
utilizing wire bonding for electrical connections between substrates
Data Source
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AI summary
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.