Variable Resistive Memory Device Matrix Design
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Solution Overview
Problem
Flash memory devices have reached scaling limits due to the need for high-capacity transistors and thick tunneling oxide films for reliable data retention, limiting their further miniaturization and performance enhancement.
Innovation Solution
A variable resistive memory device with a matrix arrangement of memory cells, each comprising a variable resistor and a selection device, connected to common and selection lines to apply specific voltages for data storage and retrieval, allowing for independent selection and reduced voltage drop and signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory uses high-capacity transistors and thick tunneling oxide films for reliable data retention, then data retention reliability is improved, but device scaling and miniaturization are limited
Solution Approach 1:
The patent changes the fundamental operating principle from charge storage in transistors to resistive switching in variable resistive materials. This parameter change allows miniaturization while maintaining reliability through the bi-stable resistance states of the variable resistive material, which can be reliably switched between high and low resistance states regardless of device size.
Solution Approach 2:
The patent replaces the mechanical/electrical system of hot carrier injection and charge storage in flash memory with an electrical field-driven resistive switching mechanism. The variable resistive material undergoes resistance state changes through applied electrical pulses, eliminating the need for complex transistor structures and thick tunneling oxide films.
2Quantity of substance
If variable resistive memory uses matrix arrangement with selection devices, then memory density is improved, but voltage drop and signal delay increase
Solution Approach 1:
The patent implements equipotentiality by connecting all memory cells in a column to a common word line that is driven to a uniform voltage level. This ensures that selected memory cells experience consistent voltage conditions, reducing signal delay variations and voltage drop effects across the memory array.
Solution Approach 2:
The patent introduces selection devices as intermediary elements between the word lines/bit lines and the variable resistive memory elements. These selection devices act as controlled switches that isolate non-selected cells from signal propagation, reducing unwanted voltage drops and signal interference while enabling dense matrix arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed memory operations with reduced voltage drop and signal delay, facilitating the miniaturization and reliability of memory devices beyond traditional flash memory limits.
Implementation Method 1
a variable resistive material layer 154 disposed between the first electrode layer 152 and the second electrode layer 156
Data Source
AI summary
Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged in the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines.