TFT Substrate Contact Hole Design Prevents Wiring Erosion
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Solution Overview
Problem
The formation of crevices at the steps in multilayer gate and data wiring structures in TFT substrates during metal deposition leads to erosion from cleaning liquids, resulting in faulty pixels in liquid crystal displays.
Innovation Solution
The design of a TFT substrate with a storage electrode line and passivation layer configuration that prevents the formation of crevices by ensuring the contact hole does not expose the step of the storage electrode line, thereby preventing cleaning liquid permeation and erosion of the data and gate wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multilayer structure is used for gate wiring and data wiring, then the functionality and signal transmission capability are improved, but crevices form at the steps during metal deposition, leading to erosion from cleaning liquids and faulty pixels
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer before the cleaning process to prevent crevice formation. The planarization layer is deposited in advance to fill and smooth the step regions created by multilayer wiring structures, thereby preventing cleaning liquid from penetrating into crevices and eroding the wiring during subsequent cleaning processes.
2Reliability
If metal material is deposited to form data wiring, then the electrical connectivity is improved, but the metal material cannot be deposited on the step, resulting in crevice formation
Solution Approach 1:
The planarization layer is formed preliminarily to create a flat surface before metal deposition. This preliminary planarization ensures that subsequent metal layers can be uniformly deposited without forming crevices at step regions, thereby improving both electrical connectivity and manufacturing precision.
Solution Approach 2:
The planarization layer acts as an intermediary between the underlying multilayer structure and the metal wiring layer. It mediates the surface irregularities by providing a flat interface, allowing uniform metal deposition and preventing crevice formation while maintaining electrical connectivity.
3Manufacturing precision
If cleaning processes are performed to remove contaminants, then the purity of the substrate is improved, but cleaning liquid permeates through crevices and erodes the data and gate wirings
Solution Approach 1:
The planarization layer is formed preliminarily to eliminate crevices before cleaning processes. By smoothing the surface in advance, the patent prevents cleaning liquid from penetrating into crevices and eroding wirings, thereby maintaining both substrate purity and wiring integrity during cleaning.
Solution Approach 2:
The patent converts the potential harm of cleaning liquid penetration into a benefit by using the planarization layer to redirect the cleaning liquid flow. The planarization layer transforms the crevice regions that would normally allow harmful liquid penetration into smooth surfaces that guide cleaning liquid away from sensitive wiring areas.
Data Source
AI summary
A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.