Microelectronic Assembly Reflowable Metal Bonding
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Solution Overview
Problem
Wafer-level packaging techniques face challenges in achieving a planar interface and reliable electrical interconnections between microelectronic elements, particularly in compact designs where signal propagation delays and component size are critical, such as in portable devices and data servers.
Innovation Solution
A microelectronic assembly is formed by using a microelectronic element with a dielectric layer and bond pads, paired with a second element having a low thermal expansion coefficient, where reflowable metal layers are deposited over the bond pads and dielectric layers, allowing for mechanical and electrical connection by joining the metal layers together, which compensates for dimensional tolerances and nonplanarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level packaging techniques are used to simultaneously make microelectronic assemblies with multiple chips stacked one over another, then productivity is improved by simultaneous fabrication, but manufacturing precision deteriorates due to difficulty in achieving sufficiently planar interface between wafers
Solution Approach 1:
A planarization layer is introduced as an intermediary between the first and second wafers. This layer compensates for non-planar surfaces on either wafer, enabling reliable bonding even when the wafer surfaces are not perfectly flat. The planarization layer acts as a mediator that absorbs surface irregularities and provides a planar bonding interface.
Solution Approach 2:
The invention changes the physical and chemical parameters of the bonding interface by introducing materials with specific properties (such as underfill materials with appropriate viscosity and curing characteristics). These parameter changes enable the bonding process to tolerate greater variations in surface planarity while still achieving reliable electrical and mechanical connections.
2Volume of moving object
If chips are packed more densely to reduce device size, then volume of the device is reduced, but reliability deteriorates due to increased difficulty in making reliable electrical interconnections
Solution Approach 1:
The invention transitions from two-dimensional planar interconnections to three-dimensional vertical interconnections by stacking chips one over another. This dimensional change allows for shorter interconnection paths and reduced signal propagation delays while maintaining reliable electrical connections through the use of planarization layers and underfill materials that ensure proper bonding and alignment.
Solution Approach 2:
Underfill materials are introduced as intermediaries between stacked chips to provide mechanical support, improve thermal management, and ensure reliable electrical interconnections. These materials fill the gaps between chips and provide a medium that enhances the stability and reliability of the vertical interconnections in dense three-dimensional arrangements.
3Speed
If signal propagation delays are minimized by using short interconnections, then speed is improved, but device complexity increases due to numerous I/O interconnections required
Solution Approach 1:
The invention moves interconnections from the planar (2D) domain to the vertical (3D) domain by stacking chips with bonding pads facing each other across the stack. This enables short vertical interconnection paths that minimize signal propagation delays while organizing numerous I/O connections in a compact three-dimensional structure rather than requiring extensive planar routing.
Solution Approach 2:
Multiple interconnection functions are merged into the vertical stacking architecture. The bonding pads on opposing chip surfaces are directly bonded together, combining mechanical support, electrical connection, and thermal management functions into a single integrated structure, thereby reducing the complexity associated with separate interconnection elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable, compact, and efficient electrical interconnections with reduced signal propagation delays, accommodating variations in planarity across the bonding interface, thereby enhancing the bandwidth and reducing power consumption in complex chip arrangements.
Implementation Method 1
The reflowable metal layers are heated to a temperature at which they melt and join together
Implementation Method 2
The reflowable metal layers are heated to melt and join together, mechanically and electrically connecting the microelectronic element with the second element
Data Source
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AI summary
Disclosed are a microelectronic assembly (300) of two elements (100, 200) and a method of forming same. A microelectronic element (100) includes a major surface (102), and a dielectric layer (120) and at least one bond pad (110) exposed at the major surface (102). The microelectronic element (100) may contain a plurality of active circuit elements. A first metal layer (130) is deposited overlying the at least one bond pad (110) and the dielectric layer (120). A second element (200) having a second metal layer (230) deposited thereon is provided, and the first metal layer (130) is joined with the second metal layer (230). The assembly (300) may be severed along dicing lanes (301) into individual units each including a chip.