Non-Volatile Memory Isolation Oxide Film Etching Residue Prevention
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Solution Overview
Problem
The existing methods for manufacturing non-volatile semiconductor memory devices often result in etching residues on the element isolation structure of peripheral circuitry, leading to defective circuits due to the exposure of isolation oxide films during the etching process for improving the coupling ratio of memory cells.
Innovation Solution
The method involves forming element isolation structures with an upper surface higher than the substrate surface, using a self-align process to form a polysilicon film on a silicon oxide film, and employing specific resist patterns to etch only the memory cell isolation structures, thereby preventing the etching of isolation oxide films in the peripheral circuitry and avoiding the formation of steps that lead to residues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the isolation oxide film is etched to expose the sides of control electrode to enlarge floating gate surface area, then the coupling ratio of memory cell is improved, but etching residues are formed on the element isolation structure of peripheral circuitry
Solution Approach 1:
The patent divides the substrate into memory cell regions and peripheral circuit regions, applying different treatments to each. The etching process is selectively applied only to the memory cell regions where isolation oxide films are removed to expose control electrode sides, while the peripheral circuit regions are preserved without etching, thus avoiding etching residues in non-memory areas.
Solution Approach 2:
The patent applies different structural modifications to different regions: in memory cell regions, the isolation oxide films are etched to create exposed sides for enhanced coupling, while in peripheral circuit regions, the isolation structures maintain their original form without etching, preventing harmful residues while preserving local functionality.
2Area of stationary object
If the isolation oxide film is etched by a predetermined thickness, then the surface area of floating gate electrode is enlarged, but steps are formed on the element isolation structure
Solution Approach 1:
The patent segments the processing into region-specific operations: memory cell regions undergo controlled etching to enlarge floating gate surface area by exposing control electrode sides, while peripheral circuit regions are excluded from etching, maintaining their isolation structure integrity and avoiding step formation.
Solution Approach 2:
Different structural outcomes are achieved in different regions: memory cell isolation structures are locally modified with controlled etching to create exposed sides for enhanced coupling, while peripheral circuit isolation structures maintain their original shape and height, avoiding detrimental steps.
3Ease of manufacture
If the multilayer insulation film and polysilicon film are removed from peripheral circuitry, then the gate electrode can be formed, but etching residues remain on the exposed isolation oxide film
Solution Approach 1:
The patent applies selective masking to prevent the removal of insulation films and polysilicon films in peripheral circuit regions. By using a resist pattern that covers peripheral circuits during the removal process, the isolation structures in these regions are protected from etching, thus preventing residue formation while allowing necessary processing in memory cell regions.
Solution Approach 2:
The patent performs preliminary masking of peripheral circuit regions before the removal of insulation films and polysilicon films. This preliminary protective action ensures that when subsequent etching steps are applied to remove these films, the peripheral circuit isolation structures are already protected and will not generate etching residues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the formation of etching residues in the peripheral circuitry, ensuring reliable insulation and improving the overall reliability of the non-volatile semiconductor memory device by maintaining the isolation oxide film surface at or above the substrate level during the etching and removal processes.
Implementation Method 1
a thermal oxide film 2 is formed on a silicon substrate 1
Implementation Method 2
the silicon oxide film 6 is planarized by a CMP (chemical mechanical polishing) method
Implementation Method 3
the silicon nitride film 3 is removed using hot phosphoric acid
Implementation Method 4
the thermal oxide film 2 is removed using hydrofluoric acid
Implementation Method 5
the isolation silicon oxide film 6 is selectively etched by a predetermined thickness using hydrofluoric acid
Data Source
AI summary
An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.