Dual Gate Memory Cell for 3D Array Leakage Control
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving reliable operation with acceptable threshold voltage and sub-threshold slope distributions due to limitations in bit line strip widths and aspect ratios, leading to manufacturing difficulties and sub-threshold leakage current issues.
Innovation Solution
A dual gate memory cell design with a channel body depth of less than 30 nanometers and an effective channel length greater than two-thirds the channel body depth, incorporating dielectric charge trapping structures and a gate structure that controls the channel effectively, suppressing sub-threshold leakage current and ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit line strip depth is increased to achieve higher memory density, then storage capacity is improved, but threshold voltage distribution becomes wider and reliability deteriorates
Solution Approach 1:
The bit line strip is segmented into multiple thinner strips stacked vertically, with each strip having a depth of less than 30 nanometers. This segmentation allows achieving higher storage capacity through increased stack height while maintaining acceptable threshold voltage distribution in each individual strip, thereby resolving the contradiction between storage capacity and reliability.
2Quantity of substance
If bit line strip width is decreased to increase memory density, then storage capacity is improved, but manufacturing difficulty increases due to high aspect ratios
Solution Approach 1:
The design transitions from increasing storage capacity through lateral expansion to vertical stacking of multiple thin bit line strips. By utilizing the vertical dimension with stacks of strips having depth less than 30 nanometers, the patent achieves higher memory density while maintaining manufacturable aspect ratios, as the vertical stacking approach is more feasible for manufacturing than creating extremely narrow lateral features.
3Reliability
If effective channel length is increased to suppress sub-threshold leakage current, then reliability is improved, but device area increases
Solution Approach 1:
The patent optimizes the effective channel length parameter to be greater than two-thirds the channel body depth, which suppresses sub-threshold leakage current and improves reliability. This parameter optimization allows achieving reliable operation with reduced device area compared to conventional designs that would require longer channel lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual gate memory cell design enhances the reliability and performance of three-dimensional memory devices by maintaining tight distributions of threshold voltage and sub-threshold slope, reducing dynamic power consumption, and improving manufacturing feasibility.
Implementation Method 1
dielectric charge trapping structures that include a tunneling layer, a dielectric charge trapping layer, and a blocking layer
Implementation Method 2
a gate structure which establishes an effective channel length of the cell greater than a threshold length... suppressing sub-threshold leakage current
Data Source
AI summary
A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.