OLED Display Transistor Storage Capacitor Vertical Stacking
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Solution Overview
Problem
Existing organic light emitting diode (OLED) displays face challenges in achieving high resolution and improved display quality due to limitations in the design of transistors and storage capacitors, which affect the control of grayscale and overall image emission.
Innovation Solution
The OLED display incorporates a driving semiconductor layer with a non-linear shape, such as curved or zigzag, and forms the driving gate electrode and storage capacitor on different layers, allowing for a broader driving range of gate voltage and increased size of transistors and capacitors, thereby enhancing grayscale control and image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional transistor and capacitor designs are used, then device complexity is reduced, but grayscale control precision and display quality deteriorate
Solution Approach 1:
The patent applies dimensionality change by forming the driving gate electrode and storage capacitor on different layers (separated by a second insulating layer), transitioning from a planar to a three-dimensional stacked configuration. This layered approach enables finer grayscale control while managing device complexity through vertical integration.
Solution Approach 2:
The patent segments the device structure by separating the driving gate electrode and storage capacitor into distinct layers, with the driving gate electrode on one layer and the storage capacitor on another layer separated by a second insulating layer. This segmentation allows independent optimization of each component for improved grayscale control.
2Measurement precision
If transistor and capacitor sizes are increased, then grayscale control and image quality improve, but pixel area is consumed
Solution Approach 1:
The patent utilizes vertical stacking to increase transistor and capacitor sizes in the vertical dimension rather than expanding horizontally. The driving gate electrode and storage capacitor are positioned on different layers, allowing larger component sizes without increasing pixel area footprint.
Solution Approach 2:
The patent implements nesting by placing the storage capacitor within the same pixel structure as the driving transistor, with both components stacked vertically. The storage capacitor is positioned between the substrate and the driving gate electrode, enabling compact integration that conserves pixel area while maintaining component size for grayscale control.
3Ease of manufacture
If driving gate electrode and storage capacitor are formed on the same layer, then manufacturing process is simplified, but driving range of gate voltage is limited
Solution Approach 1:
The patent transitions from same-layer to different-layer formation by positioning the driving gate electrode and storage capacitor on separate layers with a second insulating layer between them. This vertical separation expands the driving range of gate voltage while maintaining manufacturing feasibility through standard layered deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables finer control over the grayscale of light emission, leading to improved resolution and display quality by increasing the driving range of the gate voltage and simultaneously expanding the size of the driving transistor and storage capacitor.
Implementation Method 1
Electrons injected from the cathode and holes injected from the anode are bonded to each other in the organic emission layer to form excitons and light is emitted while the excitons discharge energy
Data Source
AI summary
An organic light emitting diode (OLED) display includes: a substrate; a first semiconductor layer and a second semiconductor layer separated from each other on a same surface of the substrate, a first insulating layer on the first semiconductor layer and the second semiconductor layer, a first gate electrode and a second gate electrode respectively overlapping the first semiconductor layer and the second semiconductor layer, a second insulating layer on the first gate electrode and the second gate electrode; a first storage electrode overlapping the first gate electrode on the second insulating layer, a third insulating layer on the first storage electrode, and a second storage electrode overlapping the first storage electrode on the third insulating layer.