Vertical Memory Structure Gate Extension Thickness
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Solution Overview
Problem
The increasing demand for higher integration in semiconductor devices leads to interference between data storage areas, which existing technologies have not effectively addressed, impacting the price competitiveness and performance of these devices.
Innovation Solution
A semiconductor device with a stacked structure featuring interlayer insulating layers and cell gate patterns alternately stacked on a substrate, along with a vertical memory structure that includes overlapping and extension portions, where the extension portions have a lesser vertical thickness than the overlapping portions, and a dielectric structure with protruding regions to reduce interference between data storage areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked gates is increased to improve the degree of integration, then the degree of integration is improved, but interference between data storage areas increases
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional vertical structure where gates are stacked in the vertical direction perpendicular to the substrate. This dimensional change allows for increased integration density without expanding the lateral footprint, thereby reducing interference between adjacent data storage areas while maintaining high integration.
Solution Approach 2:
The gate structure is segmented into multiple discrete gate electrodes stacked vertically, with each gate electrode separated by insulating layers. This segmentation allows independent control of each gate, reducing cross-interference between data storage areas while enabling high-density integration through the vertical stacking arrangement.
2Productivity
If gate patterns are stacked vertically to improve integration, then degree of integration is improved, but data retention characteristics deteriorate due to interference
Solution Approach 1:
Insulating layers are introduced as intermediary structures between adjacent gate electrodes in the vertical stack. These insulating layers act as mediators that electrically isolate each gate, preventing charge leakage and interference between adjacent data storage areas, thereby maintaining data retention characteristics while enabling vertical stacking for improved integration.
Solution Approach 2:
The patent applies different material properties to different regions of the gate structure. Specifically, high-k dielectric materials are used in specific regions to enhance charge storage capability and retention, while insulating layers with appropriate breakdown voltages are placed between gates. This local optimization of material properties ensures reliable data retention while maintaining the vertical stacked configuration for high integration.
Data Source
AI summary
The semiconductor device includes interlayer insulating layers, a gate pattern and a vertical memory structure. The interlayer insulating layers are stacked on the substrate to be spaced apart from each other. The gate pattern includes an overlapping portion disposed vertically between the interlayer insulating layers, and an extension portion extending from the overlapping portion in a horizontal direction parallel to an upper surface of the substrate. The vertical memory structure includes a channel semiconductor layer and a dielectric structure, the channel semiconductor layer extends in a direction perpendicular to the substrate upper surface to have side surfaces that face side surfaces of the interlayer insulating layers and a side surface of the extension portion. The dielectric structure is disposed between the channel semiconductor layer and the gate pattern and extends between the channel semiconductor layer and the interlayer insulating layers, and the extension portion has a vertical thickness less than that of the overlapping portion.