Equidistant Active Areas for Non-Volatile Memory Lithography
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Solution Overview
Problem
The continuous reduction of memory cell dimensions and pitch in non-volatile memory devices complicates the formation of contact regions, leading to irregularities in the matrix pitch and lithographic mask definition, especially when using Off-Axis lithographic techniques, resulting in dimension inconsistencies and sensitivity to projection optical aberrations.
Innovation Solution
The active areas of the memory cells are formed to be equidistant and of the same dimensions, allowing for the maintenance of a constant pitch and simplifying the lithographic definition of critical masks by forming contact regions within the matrix without reducing the polysilicon layer dimensions or distance between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell dimensions and pitch are continuously reduced to increase storage density, then storage capacity is improved, but lithographic mask definition accuracy deteriorates due to Off-Axis technique limitations and projection optical aberrations
Solution Approach 1:
The memory matrix is divided into multiple blocks, each with its own contact region. This segmentation allows each block to be independently defined by lithographic masks, reducing the cumulative impact of optical aberrations across the entire wafer and enabling better control of critical dimensions in high-density structures
Solution Approach 2:
Contact regions are formed at predetermined locations within each memory block before final cell definition. This preliminary action establishes reference points that guide subsequent lithographic steps, ensuring that even as cell dimensions are reduced, the critical alignment features remain within the resolution capabilities of Off-Axis lithography systems
2Reliability
If contact regions are inserted at regular intervals to maintain low source region resistance, then electrical performance is improved, but matrix pitch regularity deteriorates causing lithographic complexity
Solution Approach 1:
The contact region is merged with the active area structure, forming an integrated contact-active area unit rather than separate features. This merging maintains the regular pitch of the memory matrix while providing the necessary contact functionality, as the contact region becomes part of the repeating structural unit rather than an interruption of it
Solution Approach 2:
The contact region serves multiple functions: it provides electrical contact to the source region, maintains pitch regularity in the matrix, and acts as a reference feature for lithographic alignment. This multi-functionality resolves the contradiction by making the contact region beneficial rather than problematic for matrix regularity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the regularity of the matrix pitch and simplifies the lithographic process, reducing the impact of projection optical aberrations and ensuring consistent dimensions of memory cells and spaces, thereby improving the manufacturing efficiency and accuracy of non-volatile memory devices.
Implementation Method 1
The cell also comprises a second electrode, called control gate, which is capacitively coupled to the floating gate electrode through an intermediate dielectric layer, so called interpoly.
Implementation Method 2
After having formed at least one tunnel oxide layer and a first polysilicon layer on the semiconductor substrate 1
Data Source
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AI summary
A non volatile memory device is described being integrated on semiconductor substrate (11, 110) and comprising a matrix of non volatile memory cells (12, 120) organised in rows, called word lines, and columns, called bit lines, the device comprising: - a plurality of active areas (13, 130) formed on the semiconductor substrate (11, 110) comprising a first and a second group (G1, G2; G3, G4) of active areas, - the non volatile memory cells (12, 120) being integrated in the first group (G1, G3) of active areas, each non volatile memory cell (12, 120) comprising a source region, a drain region and a floating gate electrode coupled to a control gate electrode, at least one group (14, 140) of the memory cells (12, 120) sharing a common source region (15, 150) integrated on the semiconductor substrate (11, 110), the device being characterised in that: - said plurality of active areas (13, 130) are equidistant from each other, - a contact region (16, 160) is integrated in the second group (G2, G4) of active areas (13, 130) and is provided with at least one common source contact (17, 170) of said common source region (15, 150).