3D Coiling Via Structure for Impedance Matching in BGA Packages
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Solution Overview
Problem
Existing BGA packages face impedance mismatches between metal traces and via structures, leading to signal distortions and increased insertion and return losses due to inadequate impedance matching techniques, which occupy significant substrate space and degrade signal quality.
Innovation Solution
The implementation of three-dimensional coiling via structures that adjust inductance and capacitance to match impedance profiles, allowing for customizable impedance tuning by varying coil turns and configurations within the substrate, thereby reducing signal reflections and distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar two-dimensional traces are configured to create coiling for impedance matching, then impedance matching is improved, but insertion loss increases and substrate space is significantly occupied
Solution Approach 1:
The patent transitions from planar two-dimensional coiling to three-dimensional coiling structures. The via structure incorporates vertical coiling through multiple substrate layers, utilizing the third dimension (depth) to achieve impedance matching. This 3D coiling reduces the horizontal trace length required while maintaining the necessary inductance, thereby reducing conductor losses and occupying less substrate area.
Solution Approach 2:
The via structure embeds coiling within the vertical via path itself, nesting multiple turns of the conductor within the via hole and around the via axis. This nested configuration achieves the required inductance within the compact via structure rather than requiring separate external trace coils, reducing overall space occupation and trace length.
2Reliability
If traditional planar two-dimensional traces are configured to create coiling for impedance matching, then impedance matching is improved, but substrate space is significantly occupied
Solution Approach 1:
The patent transitions from planar two-dimensional coiling to three-dimensional coiling structures. The via structure incorporates vertical coiling through multiple substrate layers, utilizing the third dimension (depth) to achieve impedance matching. This 3D coiling reduces the horizontal trace length required while maintaining the necessary inductance, thereby reducing conductor losses and occupying less substrate area.
Solution Approach 2:
The via structure embeds coiling within the vertical via path itself, nesting multiple turns of the conductor within the via hole and around the via axis. This nested configuration achieves the required inductance within the compact via structure rather than requiring separate external trace coils, reducing overall space occupation and trace length.
3Reliability
If cut-outs are used around solder ball pads to increase impedance of BGA section, then impedance matching is improved, but the impedance cannot be increased enough to reach desired value
Solution Approach 1:
The patent employs multiple adjustable parameters in the 3D coiling via structure to achieve precise impedance control. These parameters include: the number of coiling turns, the coiling diameter, the via diameter, the via depth, and the spacing between coiling turns. By independently adjusting these parameters, the impedance can be fine-tuned over a wide range to match various target impedances, providing greater adaptability than cut-out methods.
Solution Approach 2:
The via structure incorporates adjustable and configurable elements that allow dynamic optimization of impedance matching. The coiling configuration can be customized based on specific impedance requirements, enabling the structure to adapt to different impedance matching scenarios rather than being fixed like traditional cut-out approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces insertion and return losses while maintaining signal quality by matching impedances across different conductor segments, utilizing minimal substrate space and improving high-speed signal transmission.
Implementation Method 1
three-dimensional coiling via structures that adjust inductance and capacitance to match impedance profiles
Implementation Method 2
adjust inductance and capacitance to match impedance profiles
Implementation Method 3
adjust inductance and capacitance to match impedance profiles
Data Source
AI summary
Methods, systems, and apparatuses are provided for three-dimensional coiling via structures. A substrate includes a plurality of insulating layers, a plurality of trace layers interleaved with the insulating layers, and a three-dimensional coiling via. The three-dimensional coiling via includes a plurality of electrically conductive traces and a plurality of electrically conductive vias through the insulating layers. The electrically conductive traces are present in at least two of the traces layers and are coupled together by the electrically conductive vias. The electrically conductive traces are arranged to form at least one partial turn around an axis through the substrate.