3D Tiled Compute and Logic Stack for Routing Congestion Relief
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Solution Overview
Problem
Current high-performance computing systems face issues with routing congestion and limited bandwidth due to saturated edge interfaces, which affect timing closure and resource utilization in data processing engines and programmable logic components.
Innovation Solution
Implementing a three-dimensional die stack with programmable logic and compute dies, where data processing engines are vertically aligned with programmable elements, enabling high-bandwidth coupling through through-silicon vias and programmable logic fabric, allowing for distributed memory and predictable latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more data processing engines communicate through an edge interface, then the system provides flexible and highly parallel computing interface, but the routing channels become saturated and routing congestion increases
Solution Approach 1:
The patent transitions from a two-dimensional edge interface architecture to a three-dimensional stacked architecture where compute dies are positioned directly above programmable logic dies. This vertical stacking creates direct interconnects through the substrate, eliminating the need for routing channels to traverse long distances through edge interfaces, thereby resolving the saturation issue while maintaining flexibility
2Productivity
If more processing elements communicate through an edge interface, then the system can utilize more resources, but latency between data processing engines and programmable logic increases
Solution Approach 1:
By stacking compute dies directly on top of programmable logic dies in a three-dimensional arrangement, the patent creates near-by connections with minimal signal travel distance. This vertical proximity eliminates the long horizontal routing paths through edge interfaces, significantly reducing latency while enabling more resources to be utilized
3Productivity
If data processing engines are positioned far from the edge interface, then more resources can be utilized, but timing closure requirements cannot be met
Solution Approach 1:
The patent positions data processing engines in the third dimension (vertically stacked) rather than only horizontally, allowing resources to be placed close to programmable logic while maintaining short signal paths. This vertical arrangement enables more resources to be utilized without compromising timing closure, as signals travel vertically through direct interconnects rather than through long horizontal routes
Data Source
AI summary
Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.